Large macro blocks, pre-designed datapaths, embedded memories and analog blocks are increasingly used in ASIC designs. However, robust algorithms for large-scale placement of such designs have only recently been considered in the literature, and improvements by over 10% per paper are still common. Large macros can be handled by traditional floorplanning, but are harder to account fol in min-cut and analytical placement. On the other hand, traditional floorplanning techniques do not scde to large numbers of objects, especially in terms of solution quality.Wepropose to integrate min-cut placement with fixed-outline 8001 planning to solve the more general placement problem, which includes cell placement, Roorplanning, mixed-size placement and achieving routability. At every step of min-cut placement, either partitioning or wirelength-driven. fixed-outline floorplanning is invoked. If the latter fails, we undo an earlier paltitioning decision, merge adjacent placement regions and re-floorplan the larger region to find a legal placement for the macros. Empirically, this framework improves the scalability and quality of results for traditional wirelengthdriven floorplanning. It has been validated on recent designs with embedded memories and accounts for routability. Additionally, we propose that free-shape rectilinear floorplilnning can be used with rough module-area estimates before synthesis.