An error-correcting unordered code and hardware support for robust asynchronous global communication

Agyekum,; Nowick,

doi:10.1109/date.2010.5456948

Cited by 8 publications

(12 citation statements)

References 20 publications

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“…2-phase protocols are edge-triggered where each transition of the acknowledge signal starts a new data transmission. 4-phase protocols are more widely used than 2-phase ones for the sake of implementation simplicity [8]. On Null 0001 00 0010 01 0100 10 1000 11 most QDI interconnects, data are transmitted using delayinsensitive (DI) codes, also named unordered codes [8][9], where 1-of-n codes are the most utilized ones.…”

Section: A Asynchronous Protocols and 4-phase Qdi Pipelinesmentioning

confidence: 99%

“…4-phase protocols are more widely used than 2-phase ones for the sake of implementation simplicity [8]. On Null 0001 00 0010 01 0100 10 1000 11 most QDI interconnects, data are transmitted using delayinsensitive (DI) codes, also named unordered codes [8][9], where 1-of-n codes are the most utilized ones. As an extensively utilized case of 1-of-n codes, the 1-of-4 code is presented in Table I.…”

Section: A Asynchronous Protocols and 4-phase Qdi Pipelinesmentioning

confidence: 99%

“…Another ECU code named Zero-Sum [8] provides both 1-bit error correction and 2-bit error detection for asynchronous links. Utilizing several fault-tolerant methods, a self-timed bundled-data link [11] is able to tolerate transient and permanent errors but introduces large area overhead due to the extra de-interleaving and Hamming decoding processes.…”

Section: Related Workmentioning

confidence: 99%

“…A systematic code [8][18] comprises of two fields: an information field and a check field. The information field contains the original data while the check field is generated from the data and can be used to recover the original data when errors occur.…”

Section: Delay Insensitive Redundant Check Coding Schemementioning

confidence: 99%

“…For arbitrary data word x j (0j<CN) in a DIRC code (x 0 , x 1 , …, x CN-1, c), it can be regenerated from the other data words and the corresponding check word c using the error correcting process g(X j ) defined in (8), where X j =(x 0 , …, x j-1 , x j+1 , …, x CN-1 , c) (0j<CN)) and x j ' is the regenerated data word of x j .…”

Section: B Dirc Coding Schemementioning

confidence: 99%

See 4 more Smart Citations

Transient Fault Tolerant QDI Interconnects Using Redundant Check Code

Zhang

Song

Garside

et al. 2013

2013 Euromicro Conference on Digital System Design

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Abstract-Asynchronous logic is a promising technology for building the chip-level interconnect of multi-core systems. However, asynchronous circuits are vulnerable to faults. This paper presents a novel scheme to improve the robustness of asynchronous systems. Our first contribution is a fault tolerant delay-insensitive redundant check coding scheme named DIRC. Using DIRC in 4-phase 1-of-n quasi-delay-insensitive (QDI) interconnects, all 1-bit and some multi-bit transient faults can be tolerated. The DIRC and the basic 4-phase 1-of-n pipeline stages are mutually exchangeable so that arbitrary basic stages can be replaced by DIRC stages to strengthen the fault-tolerance of long wires. Our second contribution, RPA, is a redundant technique to protect the acknowledge wires from transient faults -an issue that has long been disregarded by the community. The DIRC pipelines (using DIRC plus RPA) were simulated using the UMC 0.13ȝm standard cell library and compared with the basic pipelines. Detailed experimental results show that the 128-bit DIRC 1-of-4 pipeline is only 13% slower than the basic one but increases fault-tolerance hundred-folds when multi-bit transient faults are considered.

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Section: A Asynchronous Protocols and 4-phase Qdi Pipelinesmentioning

confidence: 99%

Section: A Asynchronous Protocols and 4-phase Qdi Pipelinesmentioning

confidence: 99%