Transient Fault Tolerant QDI Interconnects Using Redundant Check Code

Zhang, Guangda; Song, Wei; Garside, Jim; Navaridas, Javier; Wang, Zhiying

doi:10.1109/dsd.2013.11

Cited by 10 publications

(5 citation statements)

References 19 publications

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“…The architecture of the QDI Pipeline module with a sequence of stages is illustrated in Figure 7. The primary pipeline contains N 1-of-n data channels [29]. So, divide all the N 1-of-n data channels into G groups (G ≥ 1).…”

Section: Qdi Pipeline Module Using Dircmentioning

confidence: 99%

Fault protection of quasi-delay-insensitive pipeline models using efficient coding for asynchronous network-on-chip

Siddagangappa,

Dunthur Krishnagowda,

Tumkur Srinivas Murthy

2024

IJEECS

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<div align="center"><span>One promising approach for creating the chip-level connection of multiprocessing system on chip (MPSoC) is asynchronous logic. However, asynchronous systems are susceptible to errors. In this manuscript, the efficient fault-tolerant (FT) quasi-delay-insensitive (QDI) pipeline modules are designed using a delay-insensitive redundant check (DIRC) coding mechanism. The DIRC coding approach can tolerate single and multi-bit transient faults (TFs) in QDI-pipeline modules. The 4-phase 1-of-n coding approach incorporates DIRC-based QDI pipeline stages to strengthen the asynchronous links against TFs. The DIRC-based QDI pipeline stages are further used as asynchronous links in asynchronous network-on-chip ((NoC) for fault-free communication. The performance metrics like chip area, delay, and power parameters are evaluated in detail against different data widths for both basic unprotected and DIRC-based QDI pipeline modules. <br /> The DIRC-based QDI-pipeline module with 1-of-4 code uses only <2% chip area with a delay of 7.4 ns and power of 117 mW on Artix-7 chip for data width 128. The code rate of the proposed work decreased by 33.33% for both 1-of-2 and 1-of-4 codes in DIRC-based QDI-pipeline modules.</span></div>

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Section: Qdi Pipeline Module Using Dircmentioning

confidence: 99%

Fault protection of quasi-delay-insensitive pipeline models using efficient coding for asynchronous network-on-chip

Siddagangappa,

Dunthur Krishnagowda,

Tumkur Srinivas Murthy

2024

IJEECS

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“…Rahbaran and Steininger used the saboteurs to generate faults at gate level to compare the transient faults impact in an asynchronous processor and a synchronous one [9]. The fault tolerance of transient faults is discussed also by Zhang et al [46] and Kuang et al [47]. However, these works do not address the security and fault tolerance evaluation of TMR secure systems against resistive bridges defect, which are still the dominant defect for manufacturing process [48] and are more difficult to detect in a TMR structure due to the presence of redundancy [42].…”

Section: Fault Modelmentioning

confidence: 99%

Security and fault tolerance evaluation of TMR–QDI circuits

Abdelmalek

Ziani

Mokdad

2019

IET Information Security

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“…A permanent fault not only corrupts data, but also halts the handshake process, resulting in a deadlock. Most existing transient-fault-tolerant QDI designs [13], [14] are also deadlocked when a permanent fault happens. In this case, error syndromes cannot be easily obtained, making traditional faultdetection techniques [5], [11], [12] fail.…”

Section: B Deadlock Caused By Permanent Faultsmentioning

confidence: 99%

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults

Zhang

Song

Garside

et al. 2014

2014 20th IEEE International Symposium on Asynchronous Circuits and Systems

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Abstract-Asynchronous circuits have been used to implement Networks-on-Chip (NoCs), resulting in asynchronous NoCs where the links are usually implemented as quasi-delay-insensitive (QDI) pipelines to tolerate delay variations. With the ageing process of circuits, permanent faults may happen on links at runtime, causing both data errors and deadlocks of the network. This paper presents an asynchronous Spatial Division Multiplexing (SDM) NoC which tolerates permanent faults on the QDI links. Using a time-out mechanism, a general fault-detection technique can locate the permanent fault in the deadlocked NoC. To recover the network, a Drain&Release technique releases faultfree network resources on the deadlocked path. The SDM NoC physically divides every link and buffer into multiple independent virtual circuits. By configuring the switch allocator, the faulty virtual circuit is blocked so that it will not be allocated to any packets. The succeeding traffic requesting the same link will go through other fault-free virtual circuits and the network function is recovered. With regard to intermittent faults, the previously blocked virtual circuit can be resumed when the fault disappears. Experimental results show the asynchronous SDM NoC can detect and recover from permanent faults with reasonable overhead.

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Transient Fault Tolerant QDI Interconnects Using Redundant Check Code

Cited by 10 publications

References 19 publications

Fault protection of quasi-delay-insensitive pipeline models using efficient coding for asynchronous network-on-chip

Fault protection of quasi-delay-insensitive pipeline models using efficient coding for asynchronous network-on-chip

Security and fault tolerance evaluation of TMR–QDI circuits

An Asynchronous SDM Network-on-Chip Tolerating Permanent Faults

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