An ESOP-Based Reversible Circuit Synthesis Flow Using Simulated Annealing

Abstract

The problem of reversible circuit synthesis has become very important with increasing emphasis on low-power design and quantum computation. Many synthesis approaches for reversible circuits have been reported over the last decade. Among these approaches, those based on the exclusive-or sum-of-products (ESOP) realization of functions have been explored by many researchers because of two important reasons: large circuits can be handled, and the mapping from ESOP cubes to reversible gate netlist is fairly straightforward. This paper proposes a simulated annealing (SA)-based approach for transforming the ESOP cubes generated from Exorcism-4 tool using some cube mapping rules, followed by a strategy to map the ESOP cubes to a netlist of reversible gates. Both positive-and negative-control Toffoli gates are used for synthesis. Synthesis results on a number of reversible logic benchmarks show that for many of the cases, it is possible to get a reduction in quantum cost against the best-known methods.

Optimization of Reversible Circuits Using Gate Pair Classification

“…The reversible gate netlist obtained from the Exclusive-OR Sum of Product (ESOP)-based synthesis method presented in [21] is given as input for the optimization algorithm. A comparison of costs obtained from the optimization algorithm with different ESOP based methods [16][17][18][19]30] is presented in Table 6. First column gives the name of the benchmark circuit while the columns 2-6 indicate the quantum cost of respective benchmark circuits realized with existing ESOP-based methods [16][17][18][19]30].…”

“…A comparison of costs obtained from the optimization algorithm with different ESOP based methods [16][17][18][19]30] is presented in Table 6. First column gives the name of the benchmark circuit while the columns 2-6 indicate the quantum cost of respective benchmark circuits realized with existing ESOP-based methods [16][17][18][19]30]. Column 7 provides the quantum cost to realize that benchmark using the proposed optimization method.…”

“…For arithmetic benchmark circuits like frg2, in0,max46, etc., and large benchmark circuits like misex3, table3, etc., there is a reduction in the quantum cost. However, for some benchmarks like add6, bw, z4, etc., the optimization method results in higher quantum cost when compared to the existing ones [17][18][19]. This is because only a small number of required gate pairs is available in these benchmarks that can be transformed using the algorithm and the techniques described earlier.…”

“…However, this method involves a search for templates, which becomes complex as the circuit size increases. Rule-based optimization algorithms have been presented in [11][12][13]17], a simulated annealing-based approach using transformation rules has been developed in [18] and a shared cube-based approach is presented in [19]. In all of these approaches, a group of gates is replaced with a lesser cost gate netlist using a set of rules.…”