An Evolutionary Technique for Reducing the Duration of Reconfigurable Scan Network Test

Cantoro, Riccardo; Paolo, Luigi San; Reorda, M. Sonza; Squillero, Giovanni

doi:10.1109/ddecs.2018.00030

Cited by 10 publications

(15 citation statements)

References 11 publications

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“…AxxA AD0A (15) exploration of the network topology graph performing a depthfirst traversal of this graph. The third approach has been proposed in [13] and is referred to as evolutionary in this paper. The approach makes use of an evolutionary framework to generate a test sequence possibly able to minimize the test time.…”

Section: Dd0a (8) Observationmentioning

confidence: 99%

“…Futhermore, the number of clock cycles required to configure the network is given in column 4, while the number of clock cycles needed to apply test vectors is given in column 5. The cost of every configuration phase expressed in clock cycles has been increased by five (JTAG overhead) [13]. In addition, the same overhead has been taken into account for calculating the cost of a test phase.…”

Section: Dd0a (8) Observationmentioning

confidence: 99%

“…Data concerning the FSA approach are taken from [14]. Reported data related to the evolutionary approach are taken from [13]. For the depth-first approach, data have been newly generated on the ITC16 benchmarks by running the tool implementing the same algorithm as in [11].…”

Section: Dd0a (8) Observationmentioning

confidence: 99%

“…At the same time, the new algorithm is almost always faster than its predecessor. Experimental results on a set of benchmarks [15] demonstrate that the approach is able to generate test sequences orders of magnitude shorter than those reported in [14], [11] and [13], while always keeping the computational cost under control.…”

Section: Introductionmentioning

confidence: 95%

“…Since the design of large and complex SoCs may cause the appearance of very complex RSNs, generating an effective test even for large RSNs may turn into a computationally complex problem, and methods able to effectively scale are increasingly important. In [13] we proposed a new method facing this problem, based on evolutionary computation. Its main advantage lies in its ability to always produce a solution, no matter the RSN complexity, while the quality of the produced result (i.e., the duration of the resulting test) is never too far from the optimum, when the latter can be computed, and it is often lower than the one produced by the method described in [11].…”

Section: Introductionmentioning

confidence: 99%

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A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

Cantoro

Damljanovic

Reorda

et al. 2018

2018 IEEE International Test Conference (ITC)

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Nowadays, industries require reliable methods for accessing the instrumentations embedded within semiconductor devices. The situation led to the definition of standards, such as the IEEE 1687, for designing the required infrastructures, and the proposal of techniques to test them. So far, most of the test-generation approaches are either too computationally demanding to be applied in complex cases, or too approximate to yield high-quality tests. This paper exploits a recent idea: the state of a generic reconfigurable scan chain is modeled as a finite state automaton and a low-level fault, as an incorrect transition; it then proposes a new algorithm for generating a functional test sequence able to detect all incorrect transitions far more efficiently than previous ones. Such an algorithm is based on a greedy search, and it is able to postpone costly operations and eventually minimize their number. Experimental results on ITC'16 benchmarks demonstrate that the proposed approach is broadly applicable; has limited computational requirements; and the test sequences are order of magnitudes shorter than the ones previously generated by approximate methodologies.

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Section: Dd0a (8) Observationmentioning

confidence: 99%

Section: Dd0a (8) Observationmentioning

confidence: 99%

Section: Dd0a (8) Observationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 95%

Section: Introductionmentioning

confidence: 99%

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A New Technique to Generate Test Sequences for Reconfigurable Scan Networks

Cantoro

Damljanovic

Reorda

et al. 2018

2018 IEEE International Test Conference (ITC)

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A Complete Design-for-Test Scheme for Reconfigurable Scan Networks

2022

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Reconfigurable Scan Networks (RSNs) are widely used for accessing instruments offline during debug, test and validation, as well as for performing system-level-test and online system health monitoring. The correct operation of RSNs is essential, and RSNs have to be thoroughly tested. However, due to their inherently sequential structure and complex control dependencies, large parts of RSNs have limited observability and controllability. As a result, certain faults at the interfaces to the instruments, control primitives and scan segments remain undetected by existing test methods. In the paper at hand, Design-for-test (DfT) schemes are developed to overcome the testability problems e.g. by resynthesizing the initial design. A DfT scheme for RSNs is presented, which allows detecting all single stuck-at-faults in RSNs by using existing test generation techniques. The developed scheme analyzes and ensures the testability of all parts of RSNs, which include scan segments, control primitives, and interfaces to the instruments. Therefore, the developed scheme is referred to as a complete DfT scheme. It allows for a test integration to cover multiple fault locations can with a single efficient test sequence and to reduce overall test cost.

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