An Execution Model for Hardware/Software Compilation and its System-Level Realization

Lange, Holger; Koch, Andreas

doi:10.1109/fpl.2007.4380661

Cited by 16 publications

(20 citation statements)

References 8 publications

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“…This is done by the execution model (discussed in greater detail in [24]). [24] The ASH system [3] can switch between the SPP and a hardware accelerator (note: not an RCU, ASH targets ASICs) only at procedure boundaries shown in Fig. 1.1).…”

Section: Execution Modelmentioning

confidence: 99%

Adaptive Computing Systems and Their Design Tools

Koch

2010

Dynamically Reconfigurable Systems

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While reconfigurable adaptive computing has many proven advantages over conventional processors, in practice, it is often limited to niche applications. This situation, which we aim to resolve with our research, is often linked to the lack of programming languages for adaptive computers that are familiar to software developers. We present a compile flow capable of translating general-purpose C programs to hybrid hardware/software applications for execution on an adaptive computer and give an overview of the required advances in compiler technology as well as in computer architecture and operating system design. IntroductionAs demonstrated numerous times, reconfigurable computing can have significant advantages over conventional processors for a wide range of applications [30]. Despite these advantages, however, it is only rarely employed outside of academic settings.One of the key reasons for this discrepancy is the difficulty of actually programming a reconfigurable computer. Most commonly, this is done by designing a compute architecture for the algorithm from scratch, which is then described in a hardware design language such as VHDL or Verilog.While this approach can result in very high-performance implementations, it requires programmers to be experienced in computer architecture, digital logic design and hardware design languages. Only very few software developers actually have these skills. Thus, the power of reconfigurable computing remains unavailable to most potential users.

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Section: Execution Modelmentioning

confidence: 99%

Adaptive Computing Systems and Their Design Tools

Koch

2010

Dynamically Reconfigurable Systems

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“…We now keep all data areas of a SW executable (stack, heap and data segments) inside of a larger DMA Buffer at runtime, thus eliminating the time-consuming copy operations [37]. This also has the effect of making pointers freely interchangeable between HA and SW, which fulfills our ADDRESS requirement.…”

Section: Refined Solution: Aislementioning

confidence: 99%

“…Our test suite of programs (described in greater detail in [37]) contains both desktop and embedded applications:…”

Section: Fastlane+mentioning

confidence: 99%

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Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

Lange

Koch

2010

IEEE Trans. Comput.

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Abstract-We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator (HA), the latter having full master-mode access to memory. We then describe how the resulting requirements can actually be realized efficiently in a custom computer by hardware architecture and system software measures. One of these is a low-latency HA-to-GPP signaling scheme with latency up to 23x times shorter than conventional approaches. Another one is a high-bandwidth shared memory interface that does not interfere with time-critical operating system functions executing on the GPP, and still makes 89% of the physical memory bandwidth available to the HA. Finally, we show two schemes with different flexibility / performance trade-offs for running the HA in protected virtual memory scenarios. All of the techniques and their interactions are evaluated at the system level using the full-scale virtual memory variant of the Linux operating system on actual hardware.

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“…If they can actually serve multiple ports, they often have only very limited buffers (e.g., holding a DRAM row) as port-local storage. In contrast, MARC I [15] already gave multiple independent memory ports a coherent view of a shared multi-bank multi-port cache, allowing up to four parallel accesses. While the central shared cache avoided all coherency issues, it did not scale to larger numbers of ports and also limited the available clock frequency due to its fully-associative organization.…”

Section: Overviewmentioning

confidence: 99%