Architectures and Execution Models for Hardware/Software Compilation and Their System-Level Realization

Abstract

Abstract-We propose an execution model that orchestrates the fine-grained interaction of a conventional general-purpose processor (GPP) and a high-speed reconfigurable hardware accelerator (HA), the latter having full master-mode access to memory. We then describe how the resulting requirements can actually be realized efficiently in a custom computer by hardware architecture and system software measures. One of these is a low-latency HA-to-GPP signaling scheme with latency up to 23x times shorter than conventional approaches. Another one is a high-bandwidth shared memory interface that does not interfere with time-critical operating system functions executing on the GPP, and still makes 89% of the physical memory bandwidth available to the HA. Finally, we show two schemes with different flexibility / performance trade-offs for running the HA in protected virtual memory scenarios. All of the techniques and their interactions are evaluated at the system level using the full-scale virtual memory variant of the Linux operating system on actual hardware.

MARC II: A parametrized speculative multi-ported memory subsystem for reconfigurable computers

“…We modified the Reference Design by inserting the TechMod into the MCI bus between PowerPC and external 200 MHz DDR2-SDRAM main memory. The GPP can thus access the HA in a simple memory mapped fashion, while the 100 MHz HA can directly access main memory, following our FastLane architecture [16] of giving the GPP priority over the HA to ensure stable system operation. The system was implemented using Xilinx EDK and ISE 10.3, and Synplify Premier DP 9.6.1.…”

“…While explored mostly for GPPs [13], [17], [21], speculative execution is not limited to that domain [3] and can also be used in the parallel paradigms used for HAs [16].…”

Low-latency double-precision floating-point division for FPGAs

“…As target platform, we employ a Xilinx ML507 board (Virtex-5 FX-based), using the hardware and software environment described in [16] to achieve high-throughput low-latency access to shared memory between the accelerator(s) and the general-purpose PowerPC 440 processor. As the XC5VFX70T device on the actual board is too small to hold the complete system-on-chip (processor buses, memory controller, network interface, etc.)…”

Widening the Memory Bottleneck by Automatically-Compiled Application-Specific Speculation Mechanisms

“…At this level, the loop has been encapsulated as a single operation. When it detects the loop termination condition, it signals the end of hardware execution to the hardware/software interface layer [16] and passes back the computed factorial from hardware to software. Since we compile for the ACS target to a fully spatial hardware implementation with no operator reuse, we can employ a variant of the classical As-Soon-AsPossible (ASAP) static scheduling algorithm [21], adding just minor extensions to obey explicit constraints (discussed in Section 4.4).…”