Abstract. With increasing complexity of sensor network applications, the trade-off between node-local processing and transmission of data to a central node for handling becomes more significant. For distributed structural health monitoring applications (SHM), we consider different realization choices of the underlying wireless sensor network and implement a key part of the application (a high-order filter) on the novel HaLoMote architecture, a reconfigurable wireless sensor node (rWSN) with FPGAbased processing capability. We compare different tool flows supporting development of algorithms above the RTL regarding to achievable area and energy efficiency and outline the advantage of rWSN over traditional MCU-and DSP-based sensor systems in this scenario.

No abstract

Abstract-With growing FPGA capacities, applications requiring more intensive use of floating-point arithmetic become feasible candidates for acceleration using reconfigurable logic. Still among the more uncommon operations, however, are fast double-precision divider units. Since our application domain (acceleration of custom-compiled convex solvers) heavily relies on these blocks, we have implemented low-latency dividers based on the Goldschmidt algorithm that are accurate up to 1 bit of least precision (1-ULP). On Virtex-6 devices, our units operate at 200 MHz and significantly outperform other state-of-the-art 1-ULP dividers. We evaluate our blocks both stand-alone, as well as on the application-level when used for the high-level synthesis of the convex solver cores.

Abstract-Multiply-add operations form a crucial part of many digital signal processing and control engineering applications. Since their performance is crucial for the applicationlevel speed-up, it is worthwhile to explore a wide spectrum of implementations alternatives, trading increased area/energy usage to speed-up units on the critical path of the computation. This paper examines existing solutions and proposes two new architectures for floating-point fused multiply-adds, and also considers the impact of different in-fabric features of recent FPGA architectures. The units rely on different degrees of carry-save arithmetic improve performance by up to 2.5x over the closest state-of-the-art competitor.They are evaluated at the application level by modifying an existing high-level synthesis system to automatically insert the new units for computations on the critical path of three different convex solvers.