Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications

Engel, Andreas; Liebig, Björn; Koch, Andreas

doi:10.1007/978-3-642-19475-7_27

Cited by 15 publications

(7 citation statements)

References 8 publications

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“…In [4], the HaLoMote architecture was proposed to energy-efficiently perform more compute-intensive distributed tasks even on low-power wireless sensor nodes. This heterogeneous architecture combines a micro-controller-based radio system-on-chip (MCU), responsible for handling wireless protocols and system management, with a reconfigurable compute unit (RCU) for the hardwareacceleration of complex computations.…”

Section: Hardware-accelerated Data Compressionmentioning

confidence: 99%

“…In this work, data acquired by two different monitoring applications is losslessly compressed by a heterogeneous sensor node incorporating a low-power FPGA-based reconfigurable compute unit and a microcontroller-based radio system-on-chip [4]. The energy required for data transmission as well as for software and hardware implementations of the encoding are compared to demonstrate the benefits of hardware-accelerated data compression.…”

Section: Introductionmentioning

confidence: 99%

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Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks

Engel¹,

Koch

2014

Lecture Notes in Computer Science

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Abstract. In wireless sensor networks, the actual transmission of collected data is often the most energy-consuming operation. Frequently, it is worthwhile to spend energy aggregating the raw sensor data on the node to reduce the transmission effort. For many cases, lossless data compression can be employed as a general data aggregation method, as incompressible data (noise) generally does not carry any information worth transmitting. Nevertheless, the energy spent for data compression must be traded-off against the energy saved for transmitting the compressed data. In this work, sensor data of two real-life applications is compressed using a hardware-accelerator of the heterogeneous HaLOEWEn sensor node. The benefits of providing the node with a reconfigurable compute unit is demonstrated by comparing its energy consumption with that of of a purely software-based implementation.

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Section: Hardware-accelerated Data Compressionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks

Engel¹,

Koch

2014

Lecture Notes in Computer Science

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“…Obviously, our P/FCS-FMA units are not suitable for ultra low power operation. However, due to the much lower general energy consumption of FPGAs compared to GPGPUs and GPPs [25,26], FPGA designs using P/FCS-FMAs may still be competitive energy-wise with other implementation technologies. Furthermore, both architectures are applicable to the high-performance computing domain.…”

Section: Energy Consumptionmentioning

confidence: 99%

Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add Units and their Automatic Use in High-Level Synthesis

Liebig

Huthmann

Koch

2013

2013 IEEE International Symposium on Parallel &Amp; Distributed Processing, Workshops and PHD Forum

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Abstract-Multiply-add operations form a crucial part of many digital signal processing and control engineering applications. Since their performance is crucial for the applicationlevel speed-up, it is worthwhile to explore a wide spectrum of implementations alternatives, trading increased area/energy usage to speed-up units on the critical path of the computation. This paper examines existing solutions and proposes two new architectures for floating-point fused multiply-adds, and also considers the impact of different in-fabric features of recent FPGA architectures. The units rely on different degrees of carry-save arithmetic improve performance by up to 2.5x over the closest state-of-the-art competitor.They are evaluated at the application level by modifying an existing high-level synthesis system to automatically insert the new units for computations on the critical path of three different convex solvers.

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“…Up to now, no design space exploration of LED on FPGAs has been published. The proposed architecture is suited for the applications where low-cost FPGAs are deployed such as FPGA-based RFID tags [15] and low-power FPGAs [38] are deployed for battery powered applications such as FPGA-based wireless sensor nodes [14]. Hence, they represents popular platforms (FPGA-based RFID tags, FPGA-based wireless sensor nodes) for lightweight cryptographic applications.…”

Section: Introductionmentioning

confidence: 99%

A Very Compact FPGA Implementation of LED and PHOTON

Anandakumar

Peyrin

Pöschmann

2014

Progress in Cryptology -- INDOCRYPT 2014

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Abstract. LED and PHOTON are new ultra-lightweight cryptographic algorithms aiming at resourceconstrained devices. In this article, we describe three different hardware architectures of the LED and PHOTON family optimized for Field-Programmable Gate Array (FPGA) devices. In the first architecture we propose a round-based implementation while the second is a fully serialized architecture performing operations on a single cell per clock cycle. Then, we propose a novel architecture that is designed with a focus on utilizing commonly available building blocks (SRL16). This new architecture, organized in a complex scheduling of the operations, seems very well suited for recent designs that use serial matrices. We implemented both the lightweight block cipher LED and the lightweight hash function PHOTON on the Xilinx FPGA series Spartan-3 (low-cost) and Artix-7 (high-end) devices and our new proposed architecture provides very competitive area-throughput trade-offs. In comparison with other recent lightweight block ciphers, the implementation results of LED show a significant improvement of hardware efficiency and we obtain the smallest known FPGA implementation (as of today) of any hash function.

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Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications

Cited by 15 publications

References 8 publications

Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks

Hardware-Accelerated Data Compression in Low-Power Wireless Sensor Networks

Architecture Exploration of High-Performance Floating-Point Fused Multiply-Add Units and their Automatic Use in High-Level Synthesis

A Very Compact FPGA Implementation of LED and PHOTON

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