An expandable column fft architecture using circuit switching networks

COBRA: a 100-MOPS single-chip programmable and expandable FFT

“…The idea of the column FFT structure is to use a column of butterfly processors ( butterfly processors) repeatedly by feeding the reordered outputs back to the inputs of the butterfly processors. The details of the column FFT processing can be found in [13]. The number of column iterations for the transformation length is , where is the radix of the butterfly operation.…”

“…Secondly, the use of switch matrix provides memory access for every datum output from the butterfly processors. By programming and reprogramming the switch matrix, the data can be easily reordered between data input and internal processing steps to most efficiently implement the constant geometry FFT algorithm [3], [13]. The COBRA chip shown in Fig.…”

“…A column FFT architecture using bit-serial structures has be proposed in the past [13]. The similarities between the COBRA architecture and the column FFT architecture in [13] include the use of a crossbar switch matrix as a central circuit-switching network and bit-serial arithmetic throughout computation. However, the COBRA chip has the following distinctive features:…”

“…As a result, the COBRA's processing time for larger transform lengths is significantly reduced. 2) The external glue logic required for expansion in [13] has been totally eliminated, making it easier to expand the COBRA chip's transform length. 3) A great deal of DFT features are incorporated into the COBRA chip.…”

A Novel Architecture of Area Efficient FFT Algorithm for FPGA Implementation

“…In this paper, we propose a novel architecture of area efficient FFT by reusing N/2 numbers of butterfly units more than once instead of using (N/2) log 2 N butterfly units once [11]. This is achieved by a time control unit which sends back the previously computed data of N/2 butterfly units to itself for (log 2 N ) − 1 times and reuses the butterfly units to complete FFT computation.…”