COBRA: a 100-MOPS single-chip programmable and expandable FFT

Abstract

This paper presents an optimized column fast Fourier transform (FFT) architecture, which utilizes bit-serial arithmetic and dynamic reconfiguration to achieve a complete overlap between computation and communication. As a result, for a clock rate of 40 MHz, the system can compute a 24-b precision 1K point complex FFT transform in 9.25 s, far surpassing the performance of any existing FFT systems.

A Parallel FFT Architecture for FPGAs

“…Multi-chip parallel FFT designs have been published [4] [5] but these focus on VLSI. At the time of the submission of this paper, two companies have released single-FPGA parallel FFT's -SiWorks and Pentek both advertise fixed-point FFT's with throughputs in the range of 400-500 Msps but provide few details on their internal architectures..…”

A High-speed Highly Pipelined 2N-point FFT Architecture For A Dual Ofdm Processor

“…9(b). [5][6][7][8][9]. Our previous dual rate FFT/IFFT architecture [5] focused on 802.11a application is used for comparison with this highly pipelined structure.…”