A High-speed Highly Pipelined 2N-point FFT Architecture For A Dual Ofdm Processor

Lin, Hsin-Lei; Chang, Robert Chen-Hao; Chen, S.-W.; Liao, C.-Y.; Wu, Chien–Heng

doi:10.1109/mixdes.2006.1706659

Cited by 8 publications

(4 citation statements)

References 9 publications

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“…In the literature, multiple MDC FFT architectures have been proposed for different parallelization. For 2-parallel data, radix-2 [3,42,50,61], radix-2 2 [26,33,56], radix-2 3 [5,33] and radix-2 4 [33] have been studied. Architectures that process 4-parallel data consider radix-2 [50], radix-4 [14,18,60,69,71,84], radix-2 2 [26,28,33], radix-2 3 [33]…”

Section: The MDC Fft Architecturementioning

confidence: 99%

A Survey on Pipelined FFT Hardware Architectures

Garrido

2021

J Sign Process Syst

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The field of pipelined FFT hardware architectures has been studied during the last 50 years. This paper is a survey that includes the main advances in the field related to architectures for complex input data and power-of-two FFT sizes. Furthermore, the paper is intended to be educational, so that the reader can learn how the architectures work. Finally, the paper divides the architectures into serial and parallel. This classification puts together those architectures that are conceived for a similar purpose and, therefore, are comparable.

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Section: The MDC Fft Architecturementioning

confidence: 99%

A Survey on Pipelined FFT Hardware Architectures

Garrido

2021

J Sign Process Syst

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“…Pipelined architecture generally gives more area overhead and consumes more power. Pipeline-based architectures based on the linear decomposition of radix-2 are available in [12][13][14][15]. These are either single-path delay feedback (SDF) or multi-path delay commutator (MDC) architectures.…”

Section: Related Workmentioning

confidence: 99%

Radix‐4 ³ based two‐dimensional FFT architecture with efficient data reordering scheme

Kala

Mathew

Jose

et al. 2018

IET Computers & Digital Techniques

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Multi-dimensional Discrete Fourier Transforms (DFTs) play an important role in signal and image processing applications. Image reconstruction is a key component in signal processing applications like medical imaging, computer vision, face recognition etc. Two dimensional fast Fourier Transform (2D FFT) and Inverse FFT plays vital role in reconstruction. In this paper we present a fast 64 × 64 point 2D FFT architecture based on radix-43 algorithm using a parallel unrolled radix-4 3 FFT as the basic block. Our radix-4 3 architecture is a memory optimized parallel architecture which computes 64-point FFT, with least execution time. Proposed architecture produces reordered output of both 64-point one dimensional (1D) FFT and 64 × 64 point 2D FFT, without using any additional hardware for reordering. The proposed architecture has been implemented in UMC 40nm CMOS technology with clock frequency of 500 MHz and area of 0.841 mm 2. The power consumption of proposed architecture is 358 mW at 500 MHz. Energy efficiency (FFTs computed per unit of energy) is 341 points/Joule. Computation time of 64 × 64 point FFT is 8.19 μs. ASIC implementation results shows better performance of proposed work in terms of computation time when compared with state-of-art implementation. Proposed architecture has also been implemented in Virtex-7 FPGA which gives comparable area.

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“…A variable-length architecture for WiMax systems that can process FFTs of 512, 1024, 2048 or 4096 points is presented in [3]. For WLAN standards, a 64-point multi-streaming architecture is proposed in [5]. A dynamic voltage and frequency scaling pipelined architecture is proposed in [6], which can process up to 8 streams in parallel.…”

Section: Introductionmentioning

confidence: 99%

A reconfigurable FFT architecture for variable-length and multi-streaming OFDM standards

Boopal

Garrido

Gustafsson

2013

2013 IEEE International Symposium on Circuits and Systems (ISCAS2013)

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Abstract-This paper presents a reconfigurable FFT architecture for variable-length and multi-streaming WiMax wireless standard. The architecture processes 1 stream of 2048-point FFT, up to 2 streams of 1024-point FFT or up to 4 streams of 512-point FFT. The architecture consists of a modified radix-2 single delay feedback (SDF) FFT. The sampling frequency of the system is varied in accordance with the FFT length. The latch-free clock gating technique is used to reduce power consumption.The proposed architecture has been synthesized for the Virtex-6 XCVLX760 FPGA. Experimental results show that the architecture achieves the throughput that is required by the WiMax standard and the design has additional features compared to the previous approaches. The design uses 1% of the total available FPGA resources and maximum clock frequency of 313.67 MHz is achieved. Furthermore, this architecture can be expanded to suit other wireless standards.

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A High-speed Highly Pipelined 2N-point FFT Architecture For A Dual Ofdm Processor

Cited by 8 publications

References 9 publications

A Survey on Pipelined FFT Hardware Architectures

A Survey on Pipelined FFT Hardware Architectures

Radix‐4 ³ based two‐dimensional FFT architecture with efficient data reordering scheme

A reconfigurable FFT architecture for variable-length and multi-streaming OFDM standards

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A High-speed Highly Pipelined 2N-point FFT Architecture For A Dual Ofdm Processor

Cited by 8 publications

References 9 publications

A Survey on Pipelined FFT Hardware Architectures

A Survey on Pipelined FFT Hardware Architectures

Radix‐4 3 based two‐dimensional FFT architecture with efficient data reordering scheme

A reconfigurable FFT architecture for variable-length and multi-streaming OFDM standards

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Radix‐4 ³ based two‐dimensional FFT architecture with efficient data reordering scheme