An experiment of burn-in time reduction based on parametric test analysis

Sumikawa, Nik; Wang, Li-C.; Abadir, Magdy S.

doi:10.1109/test.2012.6401595

Cited by 34 publications

(12 citation statements)

References 17 publications

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“…The stress conditions usually applied during burn-in (high temperature and voltage) induce a significant NBTI degradation (V th increase) [7], [16]. The method to determine the ST V th for the proposed design approach can be qualitatively explained through (break-even point) at the end of the burn-in test (at t BI = t BE in Fig.…”

Section: Proposed Approach For St Designmentioning

confidence: 99%

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NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating

Rossi

Tenentes

Khursheed

et al. 2015

2015 20th IEEE European Test Symposium (ETS)

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Abstract-In this paper we show that power gating techniques become more effective during their lifetime, since the aging of sleep transistors (STs) due to negative bias temperature instability (NBTI) drastically reduces leakage power. Based on this property, we propose an NBTI and leakage aware ST design method for reliable and energy efficient power gating. Through SPICE simulations, we show lifetime extension up to 19.9x and average leakage power reduction up to 14.4% compared to standard STs design approach without additional area overhead. Finally, when a maximum 10-year lifetime target is considered, we show that the proposed method allows multiple beneficial options compared to a standard STs design method: either to improve circuit operating frequency up to 9.53% or to reduce ST area overhead up to 18.4%.

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Section: Proposed Approach For St Designmentioning

confidence: 99%

“…This effect increases dramatically at higher operating temperature and supply voltage [7]. These conditions are typically experienced by ICs during standard burn-in test [16], which can cause significant NBTI degradation (V th increase) of the devices even for short burn-in duration (tens of hours) [7].…”

Section: Introductionmentioning

confidence: 99%

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating

Rossi

Tenentes

Khursheed

et al. 2015

2015 20th IEEE European Test Symposium (ETS)

View full text Add to dashboard Cite

show abstract

“…NBTI aging is exacerbated by high operating temperature and supply voltage. In the IC manufacturing flow, these conditions are experienced during burn-in test, which aims at stressing circuits under test in order to identify those likely to fail early in their life cycle [10]. Therefore, standard burn-in test can cause a significant NBTI degradation even for short burn-in duration [11].…”

Section: Introductionmentioning

confidence: 99%

Reliable Power Gating With NBTI Aging Benefits

Rossi

Tenentes

Yang

et al. 2016

IEEE Trans. VLSI Syst.

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“…The Cypress SRAM requires more SRAM cells than ISSI SRAM because they produce more erroneous responses. One of the major [46][47][48]. We need at least a single measurement to register CRP (both for weak and strong PUF) in a database.…”

Section: Reliability Comparisonmentioning

confidence: 99%

Systematic Correlation and Cell Neighborhood Analysis of SRAM PUF for Robust and Unique Key Generation

et al. 2017

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A physical unclonable function (PUF) is a structure that produces a unique response, with an issued challenge (input), which can be used as an identifier or a cryptographic key. SRAM PUFs create unique responses upon power up as certain SRAM cells output a "1" or "0" with high probability due to uncontrollable process variations. A current challenge in SRAM PUFs is their sensitivity to temperature and voltage variations as well as aging. It is always challenging to make SRAM PUFs reliable and unique with algorithms that isolate stable and uncorrelated bits quickly with minimal testing (enrollment). In this paper, we explore the selection of stable and uncorrelated bits through enrollment under different conditions (temperature and voltage) and also by exploiting previously undiscovered interactions between neighboring SRAM cells. We propose University of Connecticut, Storrs, CT, USA neighbor influenced cell selection algorithm (NICSA) with the help of metrics that analyze the impact of each neighboring cell and each enrollment condition. The proposed NICSA helps to identify the "best" cells and conditions for stable bit selection. Besides reliability, SRAM PUF can be less unique due to systematic correlation among chips. We study the systematic correlation between SRAMs power-up values to find the uncorrelated cells among chips for better uniqueness. We have analyzed data from 5 ISSI, 3 IDT, and 3 Cypress SRAMs and our metrics identify the best neighborhood size (16 stable neighbors) and best enrollment condition pair high temperature, high voltage, and low temperature for NICSA.

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An experiment of burn-in time reduction based on parametric test analysis

Cited by 34 publications

References 17 publications

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating

NBTI and leakage aware sleep transistor design for reliable and energy efficient power gating

Reliable Power Gating With NBTI Aging Benefits

Systematic Correlation and Cell Neighborhood Analysis of SRAM PUF for Robust and Unique Key Generation

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