An Exploratory Study on Statistical Timing Analysis and Parametric Yield Optimization

Abstract

In this paper we report a set of statistical static timing (SSTA) studies performed on a UMC test chip manufactured at 90nm process node. We employed comprehensive variation extraction techniques to prepare a complete set of input variation data for the technology node. Our studies include SSTA runs in the presence of various process variation components, comparison of SSTA results to those obtained from traditional corner flows, and statistical optimization to improve parametric yield of the design. We observed that generally traditional corner methodologies produce more pessimistic results than those obtained from the SSTA. We also noticed that it is hard to guarantee pessimism in the traditional analyses, unless all the process corner combinations are sampled.

A parametric approach for handling local variation effects in timing analysis

“…After parametric delay information is computed, the timing propagation is done similar to the one in regular statistical static timing analysis with on-chip variation [2], [5], including both systematic and local random variations. Parametric OCV method is inherited from SSTA.…”

“…In order to ensure the proper design operation across the variation space, timing verification has to be performed on all relevant combination of process and environmental parameters. The best way to handle both device and interconnect variations over their entire ranges is to use statistical static timing analysis (SSTA) [2]. However, SSTA requires a variation-aware library characterization as well as interconnect variation extraction effort which may not be available for every technology node.…”

Secure Dynamic PUF for IoT Security

“…This unique behavior can generate cryptography secure keys using differences in delay, process, frequency, and current [2]. The process variation in ICs is within die and die-to-die variations [11]. These variations are caused due unexpected and uncontrolled differences in wafers within a die or die-to-die.…”

Κυκλώματα Αριθμητικής Υπολοίπων Με Χαμηλή Κατανάλωση Και Ανοχή Σε Διακυμάνσεις Παραμέτρων

“…Για το λόγο αυτό η λύση που δόθηκε είναι η χρήση της στατιστικής ανάλυσης της καθυστέρησης SSTA (statistical time analysis) για την επίτευξη υψηλής τιµής για την απόδοση χρονισµού Ι. Κουρέτας ◭ ♦ ◮ και για αξιόπιστη ανάλυση και ϐελτίωση των κυκλωµάτων. Την τελευταία δεκαετία για την αντιµετώπιση της διακύµανσης των παραµέτρων έχουν προταθεί πολλές µέθοδοι SSTA [87,88,[88][89][90][91][92][93][94][95][96][97][98][99][100][101][102]. Σύµφωνα µε την SSTA οι καθυστερήσεις αντιµετωπίζονται ως τυχαίες µεταβλητές οι οποίες χαρακτηρίζονται από συγκεκριµένη συνάρτηση πυκνότητας πιθανότητας (PDF).…”