An Extended Approach for Online Testing of Reversible Circuits

Abstract

Reversible computing has tremendous benefits in terms of power consumption, less heat dissipation and packaging density. Because its applications are found in diverse fields including quantum computing, nanotechnology, low power CMOS designs and cryptography, Reversible computing has gained attraction of many researchers recently. In order to incorporate fault testing capability in reversible circuits, a number of offline and online approaches have been proposed. In order to extend online testability of reversible circuits, an analysis followed by a Peres gate substitution is presented here. The proposed extension has identified online testing capabilities of MCF gates and has made all available libraries including MCT+MCF, MCT+P online testable. Furthermore a conversion for parity-preserving reversible circuits is presented. Finally the paper is concluded by proposing a generic online testable substitution of n*n reversible gate.

Design and analysis of ESOP based online testable reversible SRAM array

“…In [7,8], parity preserving technique is used for online testing of circuits consisting of only k-CNOT gates or only Peres gate. But here we have shown that by replacing each gate by its parity preserving extended gate and following the steps given below any circuit consisting of any combination of basic reversible gates can be tested.…”

“…They have explained how other approaches are unnecessarily high in overhead when compared to their proposed newapproach. So, in testing our memory array we have adopted extended gates method.This paper [7] extends an existing online testing approach [8] by proposing a testable substitution of the Peres gate.…”

“…The important reversible gates used for reversible logic synthesis are Feynman Gate, Peres Gate, Fredkin gate, TR gate and Toffoli gate. For testing purpose gates like Extended Toffoli [8] and Extended Peres [7] are used.To the best of our knowledge and according to literature survey, circuits consisting of only Toffoli gates or Peres gates have been online tested using ESOP method. The novelty of the paper is the online testability of memory array for any single stuck at faults which are designed using various combinations of extended gates using ESOP method.…”