“…Geometrical variations have been earlier experimentally studied for Dirac voltage VDirac (VTH equivalent in GFETs) in [17], [18], for Rd(s) in [20]- [23], for μ in [17], [23]- [27] and for impuritiesrelated residual charge nres in [26], however, such [23], [25], [28]. For the extraction of the basic parameters of the model (VDirac-related flat-band voltage VG0, Rd(s), μ, intrinsic mobility degradation θint [29] and nres-related parameter Δ) [5] several methodologies have been proposed [29], [30] where the one presented in [29], is applied here. IV hysteresis effects are also modelled, provided that trap-affected and trap-reduced measurement setups are available [31].…”