An extraction method to determine interconnect parasitic parameters

Abstract

Interconnect parasitic parameters in integrated circuits have significant impact on circuit speed. An accurate monitoring of these parameters can help to improve interconnect performance during process development, provide information for circuit design, or give useful reference for circuit failure analysis. Existing extraction methods either are destructive (such as SEM measurement) or can determine only partial parasitic parameters (such as large capacitor measurement). In this paper, we present a new method for extracting interconnect parasitic parameters, which can simultaneously determine the interlayer and intralayer capacitances, line resistance, and effective line width. The method is based on two test patterns of a same structure with different dimensions. The structure consumes less wafer area than existing methods. The method shows good agreement with SEM measurement of dielectric thickness in both nonglobal planarized and chemical-mechanical polished processes, and gives accurate prediction of the process spread of a ring oscillator speed over a wafer.

Interconnect capacitance characterization based on charge based capacitance measurement (CBCM) technique for DFM applications

“…Hence, Intra-layer capacitance C c becomes the dominant contributor for the total capacitance [2]. Sub I Fig.1 Illustration of interconnect parasitic capacitance Two types of test method are normally used to measure interconnection capacitances, the passive test method [3] [4] and active approaches [5] [6]. The passive test method is an easy and direct approach but due to the fact that value of the line capacitance is only of the order of femto-farads, while the pad capacitance itself is out of the order of pico-farads, Even after removing the impact from pad capacitance, errors as a result of pad capacitance in the measurement could still be of the same order as the capacitance being measured.…”

An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits

“…The work of Aoyama et al [13] characterized coupling and ground capacitance using test patterns and numerical solutions, and it provided an optimization study by wire pitch to dielectric thickness ratio. The work of Chao et al [14] presented a novel extraction methodology and test pattern, with verifications on SOG and CMP processes. The work of Chen et al [15] gave a novel on-chip measurement method for small wire capacitance.…”