An FPGA Accelerator for Spiking Neural Network Simulation and Training

Abstract

Spiking Neural Networks (SNNs) have recently been employed to solve a number of machine learning problems traditionally addressed by classical Artificial Neural Networks (ANNs). SNNs are different than ANNs as they incorporate time in their computations and information is encoded in the exact timing or frequency of discrete events, spikes. SNNs promise to deliver a higher energy efficiency than ANNs, when implemented in neuromorphic hardware, due to their event-driven nature. Naturally, this different computational model they introduce, creates different design challenges for the implementation of large-scale networks and needs to be addressed by different architectures. The spiking accelerator presented here aims to facilitate and accelerate the process of developing SNNs for ML applications that are traditionally addressed by ANNs and help bridge the accuracy gap between them. It achieves a significant speedup of up to 800× for inference and up to 500× for training compared to software SNN simulations for certain set-ups.

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“…In addition to their widespread availability on the market, FPGAs offer noise robustness and, most importantly, high implementation flexibility (173). This flexibility allows, for example, for the implementation of spiking neural networks (SNNs) (174) on FPGAs to obtain low latency and energy efficiency (173,(175)(176)(177) or computing dense optic flow (178,179). A disadvantage of FPGAs with respect to CPUs or GPUs is that programming them is more burdensome.…”