An FPGA architecture for CABAC decoding in manycore systems

Osorio, Roberto R.; Bruguera, J.D.

doi:10.1109/asap.2008.4580194

Cited by 11 publications

(4 citation statements)

References 9 publications

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“…Any valuable optimization will be downscaled by the ED. Several optimization techniques were proposed in [9] using coarse-grain pipelining and [13] using FPGA. In our approach, we apply an ED pipeline similar to [9] with some modifications.…”

Section: Parallelization With Pipeliningmentioning

confidence: 99%

H.264 Macroblock Line Level Parallel Video Decoding on Embedded Multicore Processors

Baaklini

Sbeity

Niar

2012

2012 15th Euromicro Conference on Digital System Design

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The adaptation of intensive calculation algorithms made the new emerging H.264 an efficient video codec. On the other hand, embedded processors are equipped with multicore processors, thus offering additional processing power. The H.264 codec cannot benefit from this processing power in its current state. One solution is to execute the codec on different cores concurrently. H.264 codec is a complex video compression standard that is widely used in multimedia applications. In this paper, a new parallelization technique for the H.264 decoder is proposed based on Macroblock (MB) lines distribution of a video frame on a multicore architecture. A pipeline for the Entropy Decoder (ED) at the slice level is also applied in order to speed up the processing time. Simulations conducted with High Definition (HD) resolutions show an upper limit speedup of 4.7 using the Baseline profile and 3.2 using the Main profile on a 16-core embedded processor.

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Section: Parallelization With Pipeliningmentioning

confidence: 99%

H.264 Macroblock Line Level Parallel Video Decoding on Embedded Multicore Processors

Baaklini

Sbeity

Niar

2012

2012 15th Euromicro Conference on Digital System Design

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“…There are some proposals in the literature with different approaches for CABAC acceleration [17] that can be integrated in a multicore architecture. The question that remains open is what is the level of acceleration required on the CABAC engine in order to provide the level of performance for a MB-level parallel decoder.…”

Section: B Accelerating Entropy Decodingmentioning

confidence: 99%

Scalability of Macroblock-level Parallelism for H.264 Decoding

Mesa

Ramírez

Azevedo

et al. 2009

2009 15th International Conference on Parallel and Distributed Systems

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Abstract-This paper investigates the scalability of MacroBlock (MB) level parallelization of the H.264 decoder for High Definition (HD) applications. The study includes three parts. First, a formal model for predicting the maximum performance that can be obtained taking into account variable processing time of tasks and thread synchronization overhead. Second, an implementation on a real multiprocessor architecture including a comparison of different scheduling strategies and a profiling analysis for identifying the performance bottlenecks. Finally, a trace-driven simulation methodology has been used for identifying the opportunities of acceleration for removing the main bottlenecks. It includes the acceleration potential for the entropy decoding stage and thread synchronization and scheduling. Our study presents a quantitative analysis of the main bottlenecks of the application and estimates the acceleration levels that are required to make the MB-level parallel decoder scalable.

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“…Since Multiprocessor SoC (MPSoC) are becoming more and more popular in accelerating the back-end of H.264/AVC. Osorio et al [30] proposed a novel microprogrammed CABAC decoder for MPSoC based H.264/AVC Codec. Rouvinen et al [31] utilize the Transport Triggered Architecture (TTA) for implementation of CABAC.…”

Section: Asip/ise Based Cabac Acceleratorsmentioning

confidence: 99%

CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey

Jan

Jóźwiak

2009

Lecture Notes in Computer Science

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Abstract. The demands for high quality, real-time performance and multi-format video support in consumer multimedia products are ever increasing. In particular, the future multimedia systems require efficient video coding algorithms and corresponding adaptive high-performance computational platforms. The H.264/AVC video coding algorithms provide high enough compression efficiency to be utilized in these systems, and multimedia processors are able to provide the required adaptability, but the algorithms complexity demands for more efficient computing platforms. Heterogeneous (re-)configurable systems composed of multimedia processors and hardware accelerators constitute the main part of such platforms. In this paper, we survey the hardware accelerator architectures for Context-based Adaptive Binary Arithmetic Coding (CABAC) of Main and High profiles of H.264/AVC. The purpose of the survey is to deliver a critical insight in the proposed solutions, and this way facilitate further research on accelerator architectures, architecture development methods and supporting EDA tools. The architectures are analyzed, classified and compared based on the core hardware acceleration concepts, algorithmic characteristics, video resolution support and performance parameters, and some promising design directions are discussed. The comparative analysis shows that the parallel pipeline accelerator architecture seems to be the most promising.

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An FPGA architecture for CABAC decoding in manycore systems

Cited by 11 publications

References 9 publications

H.264 Macroblock Line Level Parallel Video Decoding on Embedded Multicore Processors

H.264 Macroblock Line Level Parallel Video Decoding on Embedded Multicore Processors

Scalability of Macroblock-level Parallelism for H.264 Decoding

CABAC Accelerator Architectures for Video Compression in Future Multimedia: A Survey

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