An FPGA-Based Accelerator to Speed-Up Matrix Multiplication of Floating Point Operations

Abstract

Field Programmable Gate Arrays (FPGAs) are able to provide a high computational parallelism that can be exploited to achieve high performance improvements in intensive data processing problems. In this paper our efforts were directed towards developing a PC cluster based on nodes that use FPGAs as co-processors. The target application is a floating-point large dense matrix multiplication. Experimental results for just one node of the cluster, consisting of a Xilinx Virtex 5 VLX50T with a PCI interface, showed performance improvements compared with the Intel Core2 Quad at 2.66 GHz, achieving a speed-up of 1.19 times. Other analyses in terms of frequency variation and power dissipation have been made by considering different matrix sizes running in one node of the cluster. Recently, the platform has been updated for a powerful Gidel plaftorm, the PROCe III 260E. This new platform consists of 1 FPGA Stratix III per board. In this board, it is possible to allocate up to 40 MACs per FPGA, reaching an overall speed-up of approximately 11.2 per node of the cluster when compared with the same general-purpose processor. A full example is presented in this paper.

Synchronized-transfer-level design methodology applied to hardware matrix multiplication

“…Most state-of-the-art implementations reported achieve peak throughputs ranging between 10 to 20 GFLOPS, although nearly 30 sustained GFLOPS are reported in [10] when targeting a large Virtex-V FPGA (XC5SX240T). Our implementation targets the same FPGA as [12], which permits a comparison based on identical technologies. We obtain as much as 18.1 GFLOPS with 40 PE on a Stratix-III FPGA (EP3S150), and 26.9 GFLOPS with 56 PE on a larger FPGA (EP3SE260), while also offering a good scalability.…”

“…In the field of matrix multiplication, high-performance GPU implementations will deliver as much as 393 GFLOPS [5] on high-end video cards such as Nvidia's GeForce GTX280. The FPGA implementations of matrix multiplication proposed in [6]- [12] can deliver up to 29.8 GFLOPS but their energy efficiency is better. There is a growing interest in using FPGAs as coprocessing units for hardware acceleration, but the hardware design productivity gap remains because the design and optimization of large circuits is long, complex and reserved to experienced designers.…”

Low‐precision DSP‐based floating‐point multiply‐add fused for Field Programmable Gate Arrays

“…For example, in a wide range of matrix multipliers [1, 5,17], the multiply-accumulate operation is performed using a separate FP multiplier and FP adder. Enhancements for matrix multiplications can be obtained if dedicated FP accumulators are used to add the result of FP multipliers [4,[18][19][20].…”

“…Multiply-add fused (multiplication followed by addition/ subtraction) -MAFrepresents the most common arithmetic operation in applications which require matrix/ vector multiplications or convolutions. Such applications include graphic processing, multimedia, image and video processing, DSP, scientific computing and so on [1][2][3][4][5]. Employing a dedicated hardware floating-point (FP) MAF a unit for the combined operation has several advantages compared to the solution made of two distinct units (a FP adder and a FP multiplier) [6][7][8]:…”

“…Multiply‐add fused (multiplication followed by addition/subtraction) – MAF – represents the most common arithmetic operation in applications which require matrix/vector multiplications or convolutions. Such applications include graphic processing, multimedia, image and video processing, DSP, scientific computing and so on [1–5]. Employing a dedicated hardware floating‐point (FP) MAF a unit for the combined operation has several advantages compared to the solution made of two distinct units (a FP adder and a FP multiplier) [6–8]: Increased precision – only one rounding operation is performed instead of two. Reduced latency and reduced cost – only one set of align, normalisation and rounding operations is needed. Furthermore, both FP addition and multiplication operations can be performed by a MAF unit; however, lower performance is obtained for the separate operations with respect to a FP addition/multiplier [7, 9].…”