An FPGA-Based Seed Extension IP Core for BWA-MEM DNA Alignment

Pham‐Quoc, Cuong; Kieu-Do, Binh; Thinh, Tran Ngoc

doi:10.1109/acomp.2018.00009

Cited by 7 publications

(3 citation statements)

References 15 publications

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“…Our previous work 12 can be considered as the first work in the literature that designs and implements an FPGA‐based IP core for the Seed extension phase of the BWA‐MEM algorithm. Compared to our previous work, we totally redesign the core to achieve better performance.…”

Section: Background and Related Workmentioning

confidence: 99%

A high‐performance FPGA‐based BWA‐MEM DNA sequence alignment

Pham‐Quoc

Kieu-Do

Thinh

2019

Concurrency and Computation

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Over the last decades, Bioinformatics has been being in its honeymoon phase with more and more new algorithms as well as their improvements proposed. In Bioinformatics, the sequence alignment step is considered as an integral part that directly contributes to the DNA, RNA, or protein identifications. Despite the undeniable enhancements from the provided algorithms and computing architectures in the recent years, it is still far more to state that sequence alignment has already achieved the ideal performance. In this work, we focus on one of the most perfect justifiable steps in a state-of-the-art DNA/RNA alignment algorithm, the seed extension step in the BWA-MEM algorithm. We propose a high-speed and less power consumption FPGA-based IP core that is designed in a pipeline model under various FPGA technologies. Our core is able to operate at more than 200 MHz in almost all FPGA architectures and even up to 529 MHz on a Xilinx Virtex 6 FPGA device. The core can provide speed-ups by up to 350× when compared with an Intel Core i5 general purpose processor.

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Section: Background and Related Workmentioning

confidence: 99%

A high‐performance FPGA‐based BWA‐MEM DNA sequence alignment

Pham‐Quoc

Kieu-Do

Thinh

2019

Concurrency and Computation

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“…To overcome this obstacle, we use FPGA-based hardware accelerator platforms for edge computing devices where we can exploit the computation flexibility of host processors as well as the high performance of reconfigurable fabrics [2,3]. Furthermore, although FPGAs suffer from low working frequency, they outperform GPUs in energy consumption and provide higher performance and energy-efficient than CPUs [4].…”

Section: Introductionmentioning

confidence: 99%

An FPGA-based Convolution IP Core for Deep Neural Networks Acceleration

Nguyen-Xuan

Pham‐Quoc

2022

REV J. Electron. Commun.

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The development of machine learning has madea revolution in various applications such as object detection,image/video recognition, and semantic segmentation. Neuralnetworks, a class of machine learning, play a crucial role inthis process because of their remarkable improvement overtraditional algorithms. However, neural networks are now goingdeeper and cost a significant amount of computation operations.Therefore they usually work ineffectively in edge devices thathave limited resources and low performance. In this paper, weresearch a solution to accelerate the neural network inferencephase using FPGA-based platforms. We analyze neural networkmodels, their mathematical operations, and the inference phasein various platforms. We also profile the characteristics thataffect the performance of neural network inference. Based on theanalysis, we propose an architecture to accelerate the convolutionoperation used in most neural networks and takes up most ofthe computations in networks in terms of parallelism, data reuse,and memory management. We conduct different experiments tovalidate the FPGA-based convolution core architecture as wellas to compare performance. Experimental results show that thecore is platform-independent. The core outperforms a quad-coreARM processor functioning at 1.2GHz and a 6-core Intel CPUwith speed-ups of up to 15.69 and 2.78, respectively.

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“…Naturally, processing such large-scale data sets imposes a significant computational load for many applications in bioinformatics. The new NGS techniques reduce the cost of generating a whole human genome, which in return increases the amounts of data even more [4]. Typically, NGS techniques produce millions of short reads, usually less than 200 bases in length [5].…”

Section: Introductionmentioning

confidence: 99%

Hardware acceleration of the novel two dimensional Burrows‐Wheeler Aligner algorithm with maximal exact matches seed extension kernel

Taheri

Ansari²,

Magierowski

et al. 2020

IET Circuits, Devices & Syst

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Next‐generation sequencing techniques have dramatically increased the amount of genomic data being sequenced, which calls for the acceleration of the alignment algorithms. This article proposes an FPGA‐based accelerated implementation of the seed extension kernel of the Burrows–Wheeler alignment genomic mapping algorithm. The well‐known Smith–Waterman algorithm is used during the seed extension to find the optimum alignment between the sequences. The state‐of‐the‐art architectures in the literature use one‐dimensional (1‐D) systolic arrays to fill a similarity matrix, based on the best score out of all match combinations, mismatches and gaps are computed. The cells on the same anti‐diagonal are computed in parallel in these architectures. We propose a novel 2‐dimensional architecture in which all the cells on the same rows and the same columns are computed in parallel and, thereby, significantly accelerated the process. The similarity matrix cells are computed in two phases: (1) the calculation phase and (2) error compensation phase. The calculation phase roughly approximate the cell values and the approximation error is fixed up during the error compensation phase. Our simulation results show that the proposed architecture can be up to 718x and 1.7x faster than the software execution and the 1‐D systolic arrays, respectively.

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An FPGA-Based Seed Extension IP Core for BWA-MEM DNA Alignment

Cited by 7 publications

References 15 publications

A high‐performance FPGA‐based BWA‐MEM DNA sequence alignment

A high‐performance FPGA‐based BWA‐MEM DNA sequence alignment

An FPGA-based Convolution IP Core for Deep Neural Networks Acceleration

Hardware acceleration of the novel two dimensional Burrows‐Wheeler Aligner algorithm with maximal exact matches seed extension kernel

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