An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization

Bae, Sangwoo; Cho, Yong Cheol Peter; Park, Sungho; Irick, Kevin; Jin, Yongseok; Narayanan, Vijaykrishnan

doi:10.1109/fccm.2011.41

Cited by 29 publications

(12 citation statements)

References 3 publications

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“…on GPUs). In the case of this work, there also exist highly optimized lightweight FPGA solutions [14] that imply very fast operation and low power consumption. Furthermore, there exist alternative processing models, including directly leveraging RGB-D data and foregoing the need for a mesh model.…”

Section: Summary and Future Workmentioning

confidence: 99%

The personal cockpit

Ens

Finnegan

Irani

2014

Proceedings of the SIGCHI Conference on Human Factors in Computing Systems

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Section: Summary and Future Workmentioning

confidence: 99%

The personal cockpit

Ens

Finnegan

Irani

2014

Proceedings of the SIGCHI Conference on Human Factors in Computing Systems

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“…As a result it is used in saliency computation and shows good promise in reducing complexity while achieving superior performance [14]. This algorithm uses a multi-resolution DWT as its core decomposition and therefore is a more suitable choice than other FPGA saliency implementations [15], [16] that naively follow algorithm implementations not amenable to FPGAs, e.g., by relying on external memory access [15] or by utilizing more computationally complex hardware implementations of calculations [16], such as the Gabor oriented-filter or convolution with smoothing filter. Hence, we adopted and implemented this model.…”

Section: Discussionmentioning

confidence: 99%

Power efficient dataflow design for a heterogeneous smart camera architecture

Bhowmik

Garcia

Wallace

et al. 2017

2017 Conference on Design and Architectures for Signal and Image Processing (DASIP)

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Abstract-Visual attention modelling characterises the scene to segment regions of visual interest and is increasingly being used as a pre-processing step in many computer vision applications including surveillance and security. Smart camera architectures are an emerging technology and a foundation of security and safety frameworks in modern vision systems. In this paper, we present a dataflow design of a visual saliency based camera architecture targeting a heterogeneous CPU+FPGA platform to propose a smart camera network infrastructure. The proposed design flow encompasses image processing algorithm implementation, hardware & software integration and network connectivity through a unified model. By leveraging the properties of the dataflow paradigm, we iteratively refine the algorithm specification into a deployable solution, addressing distinct requirements at each design stage: from algorithm accuracy to hardware-software interactions, real-time execution and power consumption. Our design achieved real-time run time performance and the power consumption of the optimised asynchronous design is reported at only 0.25 Watt. The resource usages on a Xilinx Zynq platform remains significantly low.

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“…Visual attention algorithms such as Attention based on Information Maximization (AIM) [8] and a bottom-up saliency model [7] have also been accelerated using FPGAs. The AIM algorithm defines the saliency of visual content as the measure of local information within a scene.…”

Section: Related Workmentioning

confidence: 99%

Accelerators for biologically-inspired attention and recognition

Park

Zhang

DeBole

et al. 2013

Proceedings of the 50th Annual Design Automation Conference

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Video and image content has begun to play a growing role in many applications, ranging from video games to autonomous self-driving vehicles. In this paper, we present accelerators for gist-based scene recognition, saliency-based attention, and HMAX-based object recognition that have multiple uses and are based on the current understanding of the vision systems found in the visual cortex of the mammalian brain. By integrating them into a two-level hierarchical system, we improve recognition accuracy and reduce computational time.Results of our accelerator prototype on a multi-FPGA system show real-time performance and high recognition accuracy with large speedups over existing CPU, GPU and FPGA implementations.

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An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization

Cited by 29 publications

References 3 publications

The personal cockpit

The personal cockpit

Power efficient dataflow design for a heterogeneous smart camera architecture

Accelerators for biologically-inspired attention and recognition

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