An FPGA implementation of motion estimation algorithm for H.264/AVC

Kthiri, Moez; Kadionik, Patrice; Lévi, H.; Loukil, Hassen; Atitallah, Ahmed Ben; Nouri, Mohammad

doi:10.1109/isvc.2010.5654826

Cited by 9 publications

(4 citation statements)

References 8 publications

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“…An architecture for intra predictions is discussed in [41]. Other building blocks such as transform, entropy encoders or decoders and motion estimation can be found in [17,18,26,33]. In [4] a codec architecture based on processor cores implemented on an FPGA is given.…”

Section: Hardware Architectures For Video Codingmentioning

confidence: 99%

Architecture of a Low Latency H.264/AVC Video Codec for Robust ML based Image Classification

Steinert

Stabernack

2022

J Sign Process Syst

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The use of neural networks is considered as the state of the art in the field of image classification. A large number of different networks are available for this purpose, which, appropriately trained, permit a high level of classification accuracy. Typically, these networks are applied to uncompressed image data, since a corresponding training was also carried out using image data of similar high quality. However, if image data contains image errors, the classification accuracy deteriorates drastically. This applies in particular to coding artifacts which occur due to image and video compression. Typical application scenarios for video compression are narrowband transmission channels for which video coding is required but a subsequent classification is to be carried out on the receiver side. In this paper we present a special H.264/Advanced Video Codec (AVC) based video codec that allows certain regions of a picture to be coded with near constant picture quality in order to allow a reliable classification using neural networks, whereas the remaining image will be coded using constant bit rate. We have combined this feature with the ability to run with lowest latency properties, which is usually also required in remote control applications scenarios. The codec has been implemented as a fully hardwired High Definition video capable hardware architecture which is suitable for Field Programmable Gate Arrays.

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Section: Hardware Architectures For Video Codingmentioning

confidence: 99%

Architecture of a Low Latency H.264/AVC Video Codec for Robust ML based Image Classification

Steinert

Stabernack

2022

J Sign Process Syst

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“…Although this option offers good performance in terms of compression ratedistortion ratio, it also presents coarse drawbacks in order to be implemented on hardware, such as a complex architecture (specially the inter-prediction stage, where motion estimation is computed), preventing its implementation on hardware resources available on-board satellites [8], or an imprecise behaviour for lossless compression, among others. Different works are available in the state-of-the-art about FPGA implementations of the H.264 encoder, but focusing in particular stages whose performance is critical, such as motion estimation [9], [10], [11], [12], the intra-prediction [13], [14], quantization [15] or the encoding [16], [17]. A full hardware implementation of the H.264 encoder in baseline profile is presented in [18], consuming the 89% of slices available in a Xilinx XC6VLX240T FPGA.…”

Section: Introductionmentioning

confidence: 99%

Adaptation of the CCSDS 123.0-B-2 Standard for RGB Video Compression

Barrios

Guerra

López

et al. 2022

IEEE J. Sel. Top. Appl. Earth Observations Remote Sensing

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The integration of video sensors on-board satellites is becoming a trend in the space industry, since they provide extra information in the temporal domain when compared with traditional remote sensing imaging acquisition equipment. The inclusion of the temporal dimension together with the constant increase of the sensor resolution supposes a challenge for onboard processing, taking into account the limited computational and storage resources on-board satellites and that it is unfeasible to directly transmit raw video to ground, due to downlink bandwidth limitations. For these reasons, on-board video compression is needed. However, the inherent complexity of the video encoders used on ground limits their implementation on environments with high constraints in terms of computational burden, area and power consumption. This work proposes an extended compression chain that implements as compression core the CCSDS-123.0-B-2 standard, originally developed for near-lossless compression of multi-and hyperspectral images. In addition, some preprocessing stages are included to manage the temporal dimension of RGB video efficiently. The proposed solution guarantees low complexity and flexibility to compress both multi-and hyperspectral images, and panchromatic and RGB video by using a single compression instance, which is adapted by adding or removing the appropriate stages. Results demonstrate the viability of this solution to be implemented on space payloads, since high compression ratios are achieved without incurring in a penalty in terms of video quality.

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“…A standardized video compression algorithm has four main features: discrete cosine transforms (DCT), coding and quantization (Q), motion compensation (MC), and entropy coding (EC). In hardware reduction methods, the motion estimation (ME) technique based on pipelined design and rapid computing of the minimum sum absolute difference (SAD) on FPGA are introduced to speed up computation [6][7] [8][9] [10]. Moreover, the hardware efficiencies of Q reduce the computation complexity [11] [12].…”

Section: Introductionmentioning

confidence: 99%

Edge Computing-Based SAT-Video Coding for Remote Sensing

et al. 2022

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This paper proposes an edge computing-based video coding implementation on an Earth observation satellite (SAT-video coding), which can encode video using limited resources and the power of mini/microsatellites. SAT-video coding proposes a hardware-related quantization (Q) function, hardware reduction of the motion estimation (ME) method, and simplified entropy coding (EC), which reduces the computation complexity. The hardware-related Q reduces hardware resource and power consumption by 72% and 55%, respectively, compared with traditional Q implementation. The hardware reduction of ME reduces resource use compared with regular ME implementation (59 % of lookup tables [LUTs] and 79% of Registers). The total number of LUTs used for the simplified EC function is also much lower than other EC hardware implementations. The SAT-video encoder IP uses fewer hardware resources, and the power consumption is estimated at 0.0894 W at a high working frequency (125 MHz). The SAT-video encoding speed is 18.95 frames per second for 2560×2560 video. Therefore, the proposed SAT-video coding is an edge computation suitable for micro/minisatellites. The coding efficiency records the highest compression ratio at 33.8, with a peak signal-to-noise ratio of 34.46 dB. With the important task of designing edge computing based on satellite video encoding, these are adequate values for remote sensing video.INDEX TERMS Video compression, remote sensing video, hardware acceleration, satellite.

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An FPGA implementation of motion estimation algorithm for H.264/AVC

Cited by 9 publications

References 8 publications

Architecture of a Low Latency H.264/AVC Video Codec for Robust ML based Image Classification

Architecture of a Low Latency H.264/AVC Video Codec for Robust ML based Image Classification

Adaptation of the CCSDS 123.0-B-2 Standard for RGB Video Compression

Edge Computing-Based SAT-Video Coding for Remote Sensing

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