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High Efficiency Video Coding (HEVC) is the newest video coding standard approved by the ISO/IEC and ITU-T in January 2013. By providing a video coding efficiency gain up to 50 % compared to H. 264/MPEG-4 AVC high profile, the complexity of the used algorithms has raised significantly. Targeting video formats with higher spatial and temporal resolutions - e.g. 4Kp60 in broadcast applications make implementing encoders and decoders a challenging task. A few software based implementations on DSPs and general purpose CPUs are known from the literature which suffer from real-time constraints, power dissipation and hardware costs of these systems. In this paper a pure hardware implementation of a Main Profile H. 265/MPEG-HEVC Full HD capable decoder is presented solving both real-time and power constraints respectively. As a first implementation approach a state-of-the-art FPGA technology is chosen as a prototyping platform. This design can be used as a starting point for an ASIC implementation(1)

The emerging market of digital 3-D film productions in HD resolution leads to the need for high-quality equipment in the production chain. The incoming video streams of the two cameras require an image rectification due to unavoidable misalignments within the stereoscopic camera setup. This rectification can either take place in postprocessing of the recorded material or it can be applied in real time during the shooting. Especially in the case of streaming and recording of live events, real-time processing is necessary and, additionally, the system has to provide a very low latency. We present a hardware image rectification engine, which supports the processing of stereo high-definition serial digital interfaces video streams with up to 1080p30 video with a latency below 1 ms. The image rectification engines for the two channels are implemented on two Altera Stratix III EP3SL340 running at 74.25 MHz. They can be controlled by the stereoscopy analysis software, which calculates the parameters required for the image rectification at runtime.

Disparity estimation is a common task in stereo vision and usually requires a high computational effort. High resolution disparity maps are necessary to provide a good image quality on autostereoscopic displays which deliver stereo content without the need for 3D glasses. In this paper, an FPGA architecture for a disparity estimation algorithm is proposed, that is capable of processing high-definition content in real-time. The resulting architecture is efficient in terms of power consumption and can be easily scaled to support higher resolutions

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