FPGA implementation of a full HD real-time HEVC main profile decoder

Engelhardt, Denis; Moller, Jan; Hahlbeck, Jan; Stabernack, Benno

doi:10.1109/tce.2014.6937333

Cited by 30 publications

(19 citation statements)

References 18 publications

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“…In fact, at the decoder side, parallel implementations often pose difficult challenges, not only because the decoder should be able to support bitstreams produced by any encoder configuration, but also because the processing platform at the decoding device often imposes highly restrictive processing capabilities. In the current state-of-the-art approaches, only rare attempts have tackled the efficient HEVC decoder implementations, but mainly for multi-core CPUs [13] and FPGA [19].…”

Section: Related Workmentioning

confidence: 99%

“…Regarding real-time HEVC decoding, a FPGA implementation was developed in [19], which can decode Full HD video sequences at 30 frames per second (with an operating frequency of 110 MHz). However, such implementations represent different compromises in terms of energy efficiency, resources utilization, and programmability, preventing a fair comparison with high-performance computing platforms, like GPU.…”

Section: Horizontalmentioning

confidence: 99%

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GPU-assisted HEVC intra decoder

Souza

Ilić

Roma

et al. 2015

J Real-Time Image Proc

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The added encoding efficiency and visual quality offered by the High Efficiency Video Coding (HEVC) standard is attained at the cost of a significant computational complexity of both the encoder and the decoder. In particular, the considerable amount of intra prediction modes that are now considered by this standard, together with the increased complexity of the adopted block coding tree structures using a larger diversity of transforms imposes demanding computational efforts that can hardly be satisfied by current general-purpose processors to attain hard real-time requirements. Furthermore, the strict data dependencies that are imposed make parallelization a difficult and hardly efficient option with conventional approaches. To circumvent this adversity, this paper exploits Graphics Processing Units (GPUs) to accelerate the intra decoding procedure in HEVC, encompassing the most demanding modules of the decoder (i.e., de-quantization, inverse transform, intra prediction, deblocking filter, and sample adaptive offset). The presented approaches comprehensively exploit both coarse and fine-grained parallelization opportunities in an integrated perspective by redesigning the execution pattern of the involved modules, while simultaneously coping with their inherent computational complexity and strict data dependencies. As a result, the proposed parallelization, which is fully compliant with the HEVC standard, has shown to be a remarkable viable approach, being capable of satisfying hard real-time requirements by processing each Ultra HD 4 K intra frame in less than 25 ms (about 40 fps).

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Section: Related Workmentioning

confidence: 99%

Section: Horizontalmentioning

confidence: 99%

GPU-assisted HEVC intra decoder

Souza

Ilić

Roma

et al. 2015

J Real-Time Image Proc

View full text Add to dashboard Cite

show abstract

“…Usually, the first stage of an application specific IC (ASIC) development is to design, implement and test all the functions on an FPGA. This approach is chosen by many researchers because it gives designers an excellent opportunity for optimizations [6]. Hardware implementation has shown better performance compared to software implementations for many applications [7].…”

Section: Introductionmentioning

confidence: 99%

Hardware Development of the In-Vehicle System Modules for the EU Emergency Call

Nader¹,

Liu²

2018

AJEEE

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This paper presents the hardware design and implementation of the in-vehicle system (IVS) for the European Union (EU) emergency call (eCall) system. Modules of the IVS are developed and implemented on a field programmable gate array (FPGA) device. The modules are simulated, synthesized, and optimized to be loaded on a reconfigurable device as a system-on-chip (SoC) for the IVS electronic device. Benchtop test is completed for testing and verification of the developed modules. The hardware architecture and interfaces are discussed. The IVS signal processing time is analyzed for multiple frequencies. A range of appropriate frequency and two hardware interfaces are proposed. A state-of-the-art FPGA design is employed as a first implementation approach for the IVS prototyping platform. This work can be used as an initial step to implement all the modules of the IVS on a single SoC chip.

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“…Usually, the first stage of an application specific IC (ASIC) development is to design, implement and test all the functions on an FPGA. This approach is chosen by many researchers because it gives designers an excellent opportunity for optimizations [8]. Hardware implementation has shown better performance compared to software implementations for many applications [9].…”

Section: Introductionmentioning

confidence: 99%

Chip Design for In-Vehicle System Transmitter

Nader¹,

Lowry²

2018

JCC

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This paper presents embedded system design of the In-Vehicle System (IVS) for the European Union (EU) emergency call (eCall) system. The IVS transmitter modules are designed, developed and implemented on a field programmable gate array (FPGA) device. The modules are simulated, synthesized, and optimized to be loaded on a reconfigurable device as a system-on-chip (SoC) for the IVS electronic device. All the modules of the transmitter are designed as a single embedded module. The bench-top test is completed for testing and verification of the developed modules. The hardware architecture and interfaces are discussed. The IVS signal processing time is analyzed for multiple frequencies. A range of appropriate frequency and two hardware interfaces are proposed. A state-of-the-art FPGA design is employed as a first implementation approach for the IVS prototyping platform. This work is used as an initial step to implement all the modules of the IVS on a single SoC chip.

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FPGA implementation of a full HD real-time HEVC main profile decoder

Cited by 30 publications

References 18 publications

GPU-assisted HEVC intra decoder

GPU-assisted HEVC intra decoder

Hardware Development of the In-Vehicle System Modules for the EU Emergency Call

Chip Design for In-Vehicle System Transmitter

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