An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking

Szplet, R.; Klepacki, K.

doi:10.1109/tim.2009.2027777

Cited by 66 publications

(24 citation statements)

References 17 publications

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“…As described, the pulse shrinking occurs because of the difference between the falling and the rising delays along the delay chain [2][3][4][5][6]. Without any bias adjustment, the pulse-shrinking mechanism with a dimension-controlled NOT gate was proposed to vary the size of the inhomogeneous (or pulse-shrinking) NOT gate to control the pulse-shrinking amount, as shown in Fig.…”

Section: Conventional Pulse-shrinking Mechanismmentioning

confidence: 99%

“…In additional to an absolute gate delay with an advanced CMOS technology, the approaches such as parallel scaled delay elements, Vernier delay lines, and time amplification can achieve a sub-gate delay resolution at the expense of circuit complexity and area. With low cost and simple circuit operation, the pulse-shrinking method has the possibility of reaching sub-gate resolution but without requiring circuit complexity [2][3][4][5][6]. When a pulse with a finite time width undergoes a pulse-shrinking unit to cause difference between the rising and the falling propagation times, the pulse width is shrinked by a small amount (i.e., time resolution).…”

Section: Introductionmentioning

confidence: 99%

“…high resolution). Several previous works applied it to reach sub-gate resolutions [4][5][6]. In this paper, an improved version with adding a simple gate is proposed to achieve better performance in resolution for time measurement.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A CMOS Pulse-Shrinking Mechanism with Improved Resolution

Chen¹,

Chen²,

You³

et al. 2017

dtetr

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Abstract.A new CMOS time measurement mechanism based on pulse shrinking applicable to time-to-digital converters (TDCs) is presented to improve resolution. In previous mechanism, the resolution was determined by controlling size ratio between an inhomogeneous and homogeneous logic gates to achieve sub-gate resolution. By only adding an inhomogeneous gate with identical size on the previous mechanism, the proposed mechanism possesses not only a resolution improvement but also a better resolution fluctuation for process and temperature variations. The proposed work was implemented in a 0.35-µm CMOS process for performance evaluation. The results demonstrated that the proposed mechanism achieves a significant resolution improvement with better resolution insensitivity to the process and temperature variations.

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Section: Conventional Pulse-shrinking Mechanismmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A CMOS Pulse-Shrinking Mechanism with Improved Resolution

Chen¹,

Chen²,

You³

et al. 2017

dtetr

View full text Add to dashboard Cite

show abstract

“…Each of PM modules may contain one or more delay lines in many different configurations. For example, to improve of the TDCs resolution may be used an vernier (Zieliński et al 2005), pulse shrinking (Zhang and Zhou 2015;Szplet and Klepacki 2010) and interpolation techniques (Jansson et al 2006) where effective resolution depends on the difference between two various LEs propagation times. In other cases, for decrease a dead time and adaptation to multichannel solutions we apply a Flash-like architecture with direct coding lines (Ugur et al 2012).…”

Section: Flash-like Tdc Architecturementioning

confidence: 99%

Optical methods of the delay cells characteristics measurements and their applications

2016

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The only efficient optical spectrum measurement in infra-red range for low light regime is based on time multiplexing. Typically low timing jitter of the single photon detector combined with fast and high precision electronics is used for photon arrival time measurement. The timing histogram can be used to determine the spectrum of the photons. The better time detection accuracy allows to obtain the more precise spectrum information. This paper proposed an optical method for the sub-picosecond time-to-digital converters characterization prefer to optimize the multi-tapped delay lines implementation process, thus yielding the converters with much improved parameters.

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“…Thus an easyimplementation, high-resolution and general purpose short time interval measurement system is realized in a single FPGA chip. The method can be used in other FPGA devices, such as some Altera chips, which are equipped with programmable delay elements and support manual placement [22].…”

Section: Improvement and Optimizationmentioning

confidence: 99%

High-resolution short time interval measurement system implemented in a single FPGA chip

2011

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This study proposes a high-resolution short time interval measurement system based on the Vernier delay line (VDL) method. It should be noted that the programmable delay elements (PDEs) in the Xilinx field programmable gate arrays (FPGAs) provide a novel realization of delay lines. The delay lines can provide an accurate delay difference of 50 ps, which is process, voltage and temperature (PVT) invariant. An excellent consistency for the delay lines can be achieved by adjusting the timing and layout to minimize the measurement errors. The resolution achieved was 58 ps. Experimental results indicate a measurement standard deviation of 36 ps, a differential nonlinearity (DNL) of 36 ps and integral nonlinearity (INL) of 14 ps. The system features high accuracy, easy implementation and low cost.short time interval measurement system, field programmable gate array, programmable delay elements, Vernier delay line Citation:Wang H, Zhang M, Liu J. High-resolution short time interval measurement system implemented in a single FPGA chip.

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An FPGA-Integrated Time-to-Digital Converter Based on Two-Stage Pulse Shrinking

Cited by 66 publications

References 17 publications

A CMOS Pulse-Shrinking Mechanism with Improved Resolution

A CMOS Pulse-Shrinking Mechanism with Improved Resolution

Optical methods of the delay cells characteristics measurements and their applications

High-resolution short time interval measurement system implemented in a single FPGA chip

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