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This paper describes the design and test results of time interval counter featuring the single-shot precision of 7.5 ps root mean square (rms) and measurement range of 1 ms. These parameters have been achieved by combining direct counting method with a two-stage interpolation within a single clock period. Both stages of interpolation are based on the use of tapped delay lines stabilized by delay locked loop mechanism. In the first stage, a coarse resolution is obtained with the aid of high frequency multiphase clock, while in the second stage a sub-gate delay resolution is achieved with the use of differential delay line. To reduce the nonlinearities of conversion and to improve the precision of measurement, a novel segmented delay line is proposed. An important feature of this segmented delay line is partial overlapping of measurement range and resulting enhancement of both resolution and precision of time interval counter. The maximum integral nonlinearity error of the fine-stage interpolators does not exceed 16 ps and 14 ps in START and STOP interpolators, respectively. These errors have been identified by statistical calibration procedure and corrected to achieve single-shot precision better than 7.5 ps (rms). The time counter is integrated in a single ASIC (Application Specific Integrated Circuit) chip using a standard cost-effective 0.35 μm CMOS (Complementary Metal Oxide Semiconductor) process.

We present the design, operation, and test results of a new time interval/delay generator that provides the resolution of 0.3 ps, jitter below 10 ps (rms), and wide delay range of 10 s. The wide range has been achieved by counting periods of a reference clock while the high resolution and low jitter have been obtained through the two-time use of inner interpolation. This interpolation, based on charging of a single capacitor, provides both the precise external trigger synchronization and accurate generation of residual time interval. A combination of both processes virtually eliminates triggering indeterminacy. The jitter between the trigger and output is below 1 ps, which ensures a high performance delay. The generator is integrated in a single application specific integrated circuit chip using a standard cost-effective 0.35 μm CMOS process.

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