An FPGA interpreter with virtual hardware management

Diessel, Oliver; Malik, Usama

doi:10.1109/ipdps.2002.1016553

Cited by 2 publications

(3 citation statements)

References 7 publications

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“…A comparison of two versions of an interpreter for Java programming language is performed in the study of Hills et al (2011), where the authors chose the versions such as visitor pattern and interpreter pattern and the comparison is carried out with respect to maintenance and execution efficiency of implementation of Java programming language. Design of an interpreter with a virtual hardware management facility is detailed by Diessel and Malik (2002), which overcomes the Field-…”

Section: Introductionmentioning

confidence: 99%

Javascript Interpreter Using Non Recursive Abstract Syntax Tree Based Stack

Patra¹,

Pattanayak

Puthal

2013

American Journal of Applied Sciences

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In a Mobile device, apart from the battery and memory, the execution time is the key design constraint for executing the scripts of complex and unstructured JavaScript in the web-browser. Abstract Syntax Tree (AST) is a better option for mobile code as it is compiled only once. Due to very recursive nature of the AST, its traversal is going to be inherently recursive. Since use of recursion is out of scope, therefore the ultimate decision would be to emulate the recursive behavior using a set of stacks. We design an algorithm for a non recursive AST based stack, a lightweight interpreter which interprets and evaluates the complex scripts of JavaScript in the allocated time period

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Section: Introductionmentioning

confidence: 99%

Javascript Interpreter Using Non Recursive Abstract Syntax Tree Based Stack

Patra¹,

Pattanayak

Puthal

2013

American Journal of Applied Sciences

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“…Prior work in the use of Circal as a behavioural specification language for FPGA circuits resulted in the development of a compiler that produced static circuit designs targeting the Xilinx XC6200 device family [6]. In order to cope with mapping large circuits to limited FPGA area, methods for virtualizing the compiled designs were investigated and resulted in the design of the interpreter reported for the XC6200 circuit model in [5]. In tandem, the compiler was re-targeted to the Xilinx Virtex family and implemented on an Annapolis Microsystem's Wildcard [15].…”

Section: Introduction and Related Workmentioning

confidence: 99%

“…These functions are described below in more detail. For a complete description of these functions, refer to [5].…”

mentioning

confidence: 99%

Resource-aware run-time elaboration of behavioural FPGA specifications

Malik

Diessel

2002 IEEE International Conference on Field-Programmable Technology, 2002. (FPT). Proceedings.

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The Circal process algebra is being used to explore the behavioural specification of systems that are mapped to field programmable logic circuits. In this paper we report on the implementation and performance of an interpreter for system specifications given in the Circal language. In contrast to the typical design flow for field programmable technology in which designs are statically partitioned, synthesised, and mapped to pre-allocated resources, in this system the specified circuits are extracted from behavioural specifications that are partitioned, elaborated, mapped, and configured at run time as control passes through them. We report on the details of a design that targets the Celoxica RC1000 co-processor and assess preliminary performance results for this implementation. The results clearly demonstrate our method is a practical approach to overcome resource constraints, particularly in applications where these change at run time. The results also establish a benchmark against which to measure future improvements and alternative methods.

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An FPGA interpreter with virtual hardware management

Abstract: Abstract

Cited by 2 publications

References 7 publications

Javascript Interpreter Using Non Recursive Abstract Syntax Tree Based Stack

Javascript Interpreter Using Non Recursive Abstract Syntax Tree Based Stack

Resource-aware run-time elaboration of behavioural FPGA specifications

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