An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier

Baesler, Malte; Voigt, Sven-Ole; Teufel, Thomas

doi:10.1109/fpl.2010.98

Cited by 9 publications

(14 citation statements)

References 5 publications

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“…Compared with the result proposed in [22], our approach achieves faster performance in terms of the total delay and worst-case minimum clock period. On average, the improvement in total delay reduction is 20.2% and in clock cycle reduction is 21.0%, with 8.7% LUTs penalty.…”

Section: Implementation Resultsmentioning

confidence: 86%

“…On average, the improvement in total delay reduction is 20.2% and in clock cycle reduction is 21.0%, with 8.7% LUTs penalty. Thus, our approach compares favorably with the architectures in [21,22]. The improvement comes in part from the use of parallel and binary operations, as well as our fast BCD additions.…”

Section: Implementation Resultsmentioning

confidence: 89%

“…Our multipliers were implemented targeting Xilinx xc5vlx330ff1760-2 and xc6vlx760ff1760-2 FPGA devices. The results of the total delay and number of LUTs usage were extracted after the synthesis and implementation and compared with those of the multipliers proposed in [21,22]. [21].…”

Section: Implementation Resultsmentioning

confidence: 99%

“…The 16 × 16-digit multiplier with 5, 6, and 7 pipeline stages was implemented targeting Virtex-5 FPGA. The results were compared with the architecture in [22] and presented in Table 3. The total delay of all pipeline stages and the worstcase clock cycle for one pipelined stage were extracted and used for speed comparison.…”

Section: Implementation Resultsmentioning

confidence: 99%

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Efficient Realization of BCD Multipliers Using FPGAs

Gao

Al-Khalili

Langlois

et al. 2017

International Journal of Reconfigurable Computing

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In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns. 1 × 1-digit multipliers used for the partial product generation are implemented directly by 4-bit binary multipliers without any code conversion. The binary results of the 1 × 1-digit multiplications are organized according to their two-digit positions to generate the 2-digit column-based partial products. A binary-decimal compressor structure is developed and used for partial product reduction. These reduced partial products are added in optimized 6-LUT BCD adders. The parallel binary operations and the improved BCD addition result in improved performance and reduced resource usage. The proposed approach was implemented on Xilinx Virtex-5 and Virtex-6 FPGAs with emphasis on the critical path delay reduction. Pipelined BCD multipliers were implemented for 4 × 4, 8 × 8, and 16 × 16-digit multipliers. Our realizations achieve an increase in speed by up to 22% and a reduction of LUT count by up to 14% over previously reported results.

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Section: Implementation Resultsmentioning

confidence: 86%

Section: Implementation Resultsmentioning

confidence: 89%

Section: Implementation Resultsmentioning

confidence: 99%

Section: Implementation Resultsmentioning

confidence: 99%

See 2 more Smart Citations

Efficient Realization of BCD Multipliers Using FPGAs

Gao

Al-Khalili

Langlois

et al. 2017

International Journal of Reconfigurable Computing

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“…Therefore, the number of leading zeros for both operands is counted, and the significands are normalized by barrel shifters. Due to performance issues, the leading zeros counter exploit the FPGA's fast carry chains, as proposed in [23].…”

Section: Ieee 754-2008 Floating-point Divisionmentioning

confidence: 99%

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Baesler

Voigt

2013

International Journal of Reconfigurable Computing

Self Cite

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Decimal floating point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper we present five different radix-10 digit recurrence dividers for FPGA architectures. The first one implements a simple restoring shift-and-subtract algorithm, whereas each of the other four implementations performs a nonrestoring digit recurrence algorithm with signed-digit redundant quotient calculation and carry-save representation of the residuals. More precisely, the quotient digit selection function of the second divider is implemented fully by means of a ROM, the quotient digit selection function of the third and fourth dividers are based on carrypropagate adders, and the fifth divider decomposes each digit into three components and requires neither a ROM nor a multiplexer. Furthermore, the fixed-point divider is extended to support IEEE 754-2008 compliant decimal floating-point division for decimal64 data format. Finally, the algorithms have been synthesized on a Xilinx Virtex-5 FPGA, and implementation results are given.

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Taxonomy of Decimal Multiplier Research

Sengupta

Sultana

2018

Algorithms and Applications

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An IEEE 754-2008 Decimal Parallel and Pipelined FPGA Floating-Point Multiplier

Cited by 9 publications

References 5 publications

Efficient Realization of BCD Multipliers Using FPGAs

Efficient Realization of BCD Multipliers Using FPGAs

Analysis of Fast Radix-10 Digit Recurrence Algorithms for Fixed-Point and Floating-Point Dividers on FPGAs

Taxonomy of Decimal Multiplier Research

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