An ILP Formulation for System-Level Application Mapping on Network Processor Architectures

Ostler,; Chatha,

doi:10.1109/date.2007.364574

Cited by 30 publications

(11 citation statements)

References 17 publications

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“…The mapping is restricted to the Xelerated processors in which the communication is based on packet buffers between the processors. Finally, in [14] a system level application mapping on network processors is presented that it is based on Integer Linear Programming (ILP). The mapping is targeting an Intel IXP network processor and again the communication is based on explicit data transfers through DMAs.…”

Section: Related Workmentioning

confidence: 99%

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform

Kachris

Nikiforos

Papaefstathiou

et al. 2013

Journal of Systems Architecture

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Section: Related Workmentioning

confidence: 99%

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform

Kachris

Nikiforos

Papaefstathiou

et al. 2013

Journal of Systems Architecture

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“…Srinivasan et al [44] present a survey on these approaches considering performance and power requirements. Another concern is the minimization of execution time of the placement algorithms with the help of ILP [37]. Srinivasan and Chatha [43] propose another ILP-based approach that takes throughput constraints into account.…”

Section: Chapter 2 Related Workmentioning

confidence: 99%

Application-Specific Heterogeneous Network-on-Chip Design

Demirbas

Akturk

Öztürk

et al. 2013

The Computer Journal

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“…The major drawback is requiring the application developer an in-depth understanding of the NP system architecture. Ostler and Chatha [15] presented an automatic ILP-based technique for application mapping on NPs, however, the effectiveness of this technique relies on accurate characterizing a process latency and its data size.…”

Section: Related Workmentioning

confidence: 99%

Mapping task graphs onto Network Processors using genetic algorithm

Weng

Kumar

Dechu

et al. 2008

2008 IEEE/ACS International Conference on Computer Systems and Applications

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Network Processors (NPs) are embedded system-on-achip multiprocessors that are optimized to perform simple packet processing tasks at data rates of several Gigabytes per second. They are the key components to build a performance-scalable and function-flexible network systems. To meet the performance demands of increasing link speeds and more complex network applications, NPs are implemented with several dozen of processor cores and run multiple packet processing applications in parallel. This trend makes it increasingly difficult for application developers to program NPs for high performance. This paper presents an automated task scheduling technique to address this parallel programming complexity.Our proposed technique is based on GA. By incorporating tasks dependency into scheduling list and encoding task scheduling list as a chromosome, GA can quickly remove the invalid mappings and evolve to the high quality solutions. This technique takes advantage of task-level and application-level parallelism to maximize system performance for a given NPs architecture. The simulation results show that this proposed technique can generate high quality mapping comparing to other heuristics by mapping some sample network applications. This work will also enable researchers and engineers to systematically evaluate and quantitatively understand the NPs system issues including application partitioning, architecture organizing, workload mapping and run-time operating.

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An ILP Formulation for System-Level Application Mapping on Network Processor Architectures

Abstract: Abstract

Cited by 30 publications

References 17 publications

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform

NP-SARC: Scalable network processing in the SARC multi-core FPGA platform

Application-Specific Heterogeneous Network-on-Chip Design

Mapping task graphs onto Network Processors using genetic algorithm

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