An improved compact model of cross-shaped horizontal CMOS-integrated Hall-effect sensor

Abstract

A new compact model of a cross-shaped horizontal integrated Hall-effect sensor is presented in this paper. Compared to existing models, the model reliability is improved, especially for designs in which the bias and the measurement circuits are not independent. The Hall device model uses six subcomponents, each modeling the non-linear resistance due to the sensor space charge region modulation and the Hall voltage. The model is implemented in VHDL-AMS and Verilog-A. It includes 10 parameters (physical parameters of the semiconductor and sensor geometry). The model gives simulation results that are in accordance with classic experimental results founded in the literature.

An Improved Equivalent Simulation Model for CMOS Integrated Hall Plates

“…In order to determine the resistance values of R H and R D in our model, a new and simple computation method is proposed in contrast to the FEM simulation method [ 7 ]. It is well known that it is best to measure the N-well sheet resistance R s according to the Van-der-Pauw method.…”

“…However, this macro model needs an accurate JEFTs device model which normally cannot be provided by the standard CMOS technology. Recently, Madec et al developed a compact model of a cross-shaped horizontal integrated Hall sensor [ 7 ]. It uses six sub-components to accurately model the non-linear resistance, allowing for the influence of space charge region modulation due to sensor bias.…”