An Improved Diffusion Based Placement Algorithm for Reducing Interconnect Demand in Congested Regions of FPGAs

Abstract

An FPGA has a finite routing capacity due to which a fair number of highly dense circuits fail to map on slightly underresourced architecture. The high-interconnect demand in the congested regions is not met by the available resources as a result of which the circuit becomes unroutable for that particular architecture. In this paper, we present a new placement approach which is based on a natural process called diffusion. Our placer attempts to minimize the routing congestion by evenly disseminating the interconnect demand across an FPGA chip. For the 20 MCNC benchmark circuits, our algorithm reduced the channel width for 15 circuits. The results showed on average ∼33% reduction in standard deviation of interconnect usage at an expense of an average ∼13% penalty on critical path delay. Maximum channel width gain of ∼33% was also observed.

An OpenCL-based parallel acceleration of aSobel edge detection algorithm Using IntelFPGA technology

“…Normally, more resources can be used to increase performance; however, this may lead to increased design complexity and critical path delay (latency) (Zheng et al, 2014). It is also not possible to expand the resource usage beyond certain percentages as this introduces the challenge of providing routing channels between connected elements/blocks (Asghar & Parvez, 2015;Vanderbauwhede & Benkrid, 2013). It is worth mentioning that there is an overhead of using OpenCL to program the FPGAs over using hardware description languages such as VHDL in terms of resource usage.…”

Mapping large-scale systems on to high density FPGAs

“…However, this approach lacks a method to determine localized congestion. A diffusion based routability driven placement approach is introduced in [73] with similar cost functions. Local congestion cost in this approach, is determined by the ratio of occupancy of two CLBs to the distance between the two.…”