International audienceAn application specific inflexible FPGA (ASIF) is an FPGA with reduced flexibility that can implement a set of application circuits which will operate at mutually exclusive times. These circuits are efficiently placed and routed on an FPGA to minimize the total routing switches required by the architecture. Later all the unused routing switches are removed from the FPGA to generate an ASIF. An ASIF for a set of 17 MCNC benchmark circuits is found to be 5.43 times (81.5%) smaller than a mesh-based unidirectional FPGA required to map any of these circuits

International audienceThis book concerns the broad domain of reconfigurable architectures and more specifically FPGAs. Different issues that are the centre of this book are very essential and are intended to overcome the current limitations of FPGAs, which are experiencing extremely rapid and sustained development for several years. In fact, FPGAs offer a particularly remarkable flexibility but suffer from a level of performance that can be disadvantageous for some applications in terms of surface, speed or energy. This work presents several significant and original contributions in order to remove these limitations by focusing especially on the surface metric. This book aims at exploring heterogeneous FPGA architectures dedicated to a given set of application circuits. Beyond architecture exploration, this work also presents automatic FPGA "layout" generation flow, and a new component called as an ASIF "Application Specific Inflexible FPGA", which significantly reduces silicon footprint by customizing the architecture for a given set of applications circuits. The importance and originality of the contributions made in this work revolve around this new concept of application specific reconfigurable circuits, mainly the development of an entire design environment including: generation tools, floor-planning, placement and routing adapted to the case of heterogeneous blocks. Careful analysis of results and the validation of proposed techniques have also been observed. The monograph of this book is based on Husain’s doctoral thesis. It was a great pleasure for me to supervise his thesis. This book will be of special interest for students and researches in the domain of FPGA architectures in general, and application-specific FPGA architectures, heterogeneous FPGA architectures, and their automatic hardware generation in particular

International audienceAn application specific FPGA (ASIF) is an FPGA with reduced flexibility and improved density. A heterogeneous ASIF is reduced from a heterogeneous FPGA for a predefined set of applications. This work presents a new tree-based heterogeneous ASIF and uses two sets of open core benchmarks to explore the effect of lookup table (LUT) and arity size on it. For tree-based ASIF, LUT size is varied from 3 to 7 while arity size is varied from 4 to 8 and 16. Experimental results show that smaller LUTs with higher arity sizes produce good area results. However, smaller LUTs produce worse results in terms of delay. Further experimental results show that for tree-based ASIF, the combination LUT 4 with arity 16 for SET I and LUT 3 with arity 16 for SET II gives best results in terms of area-delay product. Area comparison between mesh and tree-based ASIFs shows that tree-based ASIF gives 11.27% routing area gain for SET I and gives almost same area results for SET II while consuming 70.30% and 69.80% less wires for SET I and SET II benchmarks respectively. Finally the quality analysis shows that tree-based ASIF produces around 18% better results compared to mesh-based ASIF

International audienceAn Application Specific Inflexible FPGA (ASIF) [12] is an FPGA with reduced flexibility that can implement a set of application circuits which will operate at different times. Application circuits are efficiently placed and routed on an FPGA in such a way that total routing switches used in the FPGA architecture are minimized. Later all unused routing resources are removed from the FPGA to generate an ASIF. An ASIF which is reduced from a heterogeneous FPGA (i.e. containing hard-blocks such as Multipliers, Adders and RAMS etc) is called as a Heterogeneous-ASIF. This work shows that a standard-cell based Heterogeneous-ASIF using Multipliers, Adders and Look-Up-Tables for a set of 10 opencores application circuits is 85% smaller in area than a single driver FPGA using the same blocks, and only 24% larger than the sum of areas of their standard-cell based ASIC version. If the Look-Up-Tables are replaced with a set of repeatedly used hard logic gates (such as AND gate, OR gate, flip-flops etc), the ASIF becomes 89% smaller than the Look-Up-Table based FPGA and 3% smaller than the sum of ASICs. The area gap between ASIF and sum of ASICs can be further reduced if repeatedly used groups of standard-cell logic gates in an ASIF are designed in full-custom. One of the major advantages of an ASIF is that just like an FPGA, an ASIF can also be reprogrammed to execute new or modified circuits, but at a very limited scale. A new CAD flow is presented to map application circuits on an ASIF

Mesh-based heterogeneous FPGAs are commonly used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks are arranged in fixed columns as they offer an easy and compact layout. However, the placement of hard-blocks in fixed columns can potentially lead to underutilization of logic and routing resources and this problem is further aggravated with increase in the types of hard-blocks. This work explores and compares different floor-planning techniques of mesh-based FPGA to determine their effect on the area, performance, and power of the architecture. A tree-based architecture is also presented; unlike mesh-based architecture, the floor-planning of heterogeneous tree-based architecture does not affect its routing requirements due to its hierarchical structure. Both mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.