Exploration of Heterogeneous FPGA Architectures

Abstract

Mesh-based heterogeneous FPGAs are commonly used in industry and academia due to their area, speed, and power benefits over their homogeneous counterparts. These FPGAs contain a mixture of logic blocks and hard blocks where hard blocks are arranged in fixed columns as they offer an easy and compact layout. However, the placement of hard-blocks in fixed columns can potentially lead to underutilization of logic and routing resources and this problem is further aggravated with increase in the types of hard-blocks. This work explores and compares different floor-planning techniques of mesh-based FPGA to determine their effect on the area, performance, and power of the architecture. A tree-based architecture is also presented; unlike mesh-based architecture, the floor-planning of heterogeneous tree-based architecture does not affect its routing requirements due to its hierarchical structure. Both mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

Design and optimization of heterogeneous tree-based FPGA using 3D technology

“…Since the benchmark circuits plays a major role in the FPGA exploration, three sets of benchmarks [11] were chosen based on trends of communication between different blocks. In order to validate the improvements in critical path delay, we used a 3D Tree-based FPGA architecture with seven-levels and arity 4, (4x4x4x4x4x4x4) with full connectivity for each SET of benchmarks.…”

“…While designing 3D heterogeneous Tree-based FPGA, we used the white space available at tier 0 layer to stack Hard-blocks at multiple levels of BFT-based tree interconnect network. Previous experiments conducted in our laboratory lead to the conclusion that, placing hard-blocks at higher levels of the Tree-based multilevel interconnect network can lead to a better trade-off between area and speed of 3D FPGAs [11].…”

Three-Dimensional Tree-Based FPGA: Architecture Exploration Tools and Technologies

“…Since the benchmark circuits plays a major role in the heterogeneous FPGA exploration, three sets of benchmarks [11,[22][23][24][25] were chosen based on trends of communication between different types of hard-blocks. Generally in academia and industry, the quality of an FPGA architecture is measured by mapping a certain set of benchmarks on it.…”

“…These benchmarks are shown in Tables 6.3, 6.4 and 6.5. Benchmarks shown in Table 6.3 are developed at [22], the benchmarks shown in Table 6.4 are obtained from [24] and the benchmarks shown in Table 6 In SET I benchmarks, the major percentage of total communication is between HBs (i.e. HB-HB) and only a small part of total communication is covered by the communication CLB-CLB or CLB-HB.…”

A novel heterogeneous FPGA architecture based on memristor-transistor hybrid approach

“…In order to narrow the gap between FPGAs and ASICs, heterogeneous FPGAs have emerged as an attractive solution for implementation of complex applications. Heterogeneous FPGAs with embedded Hard-Blocks (HBs) like adders, multipliers have shown significant improvement over homogeneous FPGAs [2]- [4]. Some of known examples of commercial heterogeneous FPGAs include Xilinx's Virtex [5] and Altera's Stratix family [6].…”