An Improved Mesh Topology and Its Routing Algorithm for NoC

Abstract

Network on chip (NoC) is an effective solution to complex on-chip communication problem. The mesh topology is one of the most popular NoC. It has completely regular topology which can be implemented easily, but the communication delay between remote nodes is large. In this paper, we propose an improved topology called Tmesh, which is based on the standard mesh network by inserting four long links. We also present a deadlock-free routing algorithm for Tmesh named TXY algorithm. Indeed, our experimental results demonstrate a certain reduction in the average packet delay and routing hops. Keywords-mesh; routing algorithm; NoC I. INTRODUCTIONContinuous scaling of CMOS technology makes it possible to integrate a large number of cores on a chip multiprocessor (CMP) system. As a result, inter-core connection and communication becomes an important factor that affecting processor performance. Now there are three interconnection manners for CMP, which are bus, cross-switch and NoC [1][2][3][4][5]. When the number of cores is small, bus and cross-switch can satisfy the communication requirements. As the number of cores increasing, bus can not effectively deal with multiple data stream's concurrent transmission, and cross-switch causes exponential growth of hardware overhead. NoC becomes an effective solution to the interconnection of many cores.Compared with bus and cross-switch, NoC is based on macro computer network and has better reusability and scalability. At present, much research is based on mesh, torus topology, especially the mesh. Mesh is easy for physical implement and routing. It has been applied in practical design, such as Godson-3[5], TILE64 Processor [6]. However, it has large communication delay between remote nodes, increasing the possibility of network congestion [7]. Ogras proposed a method to optimize the performance of NoC [8], by inserting a few additional long-range links in mesh topology to reduce the communication delay between some nodes. This paper presents an improved mesh topology called Tmesh based on the above idea. We also give a routing algorithm named TXY algorithm. The experimental results demonstrate a certain reduction in the average packet delay and routing hops. When the network has 8×8 nodes, the average delay and routing hops of Tmesh are 2.92% and 3.53% lower than those of mesh respectively. This paper is organized as follows. In Section II, we describe Tmesh topology, and compare it with mesh from the network diameter, the ideal throughput and the ideal average delay. In Section III, present a routing algorithm for Tmesh and discuss the strategy of deadlock avoidance. In Section IV, the simulation environment and the performance analysis is given. Section V concludes the paper and indicates possible directions for future work.

FTTCR: A New Interconnection Architecture for Parallel Systems

“…There are other topologies like DiaTorus [11], Dmesh [12], Diametric mesh [13], Tmesh [14], xmesh, xtorus and xxtorus [15], CBP-Mesh and CBP Torus [16,17] have no uniform degree and the number of links is also more. The new torus network, which has the hypercube Q3 as the basic module has been proposed [18].…”

DIA-TORUS:A Novel Topology for Network on Chip Design

“…The complexity of router implementation depends on the degree of the router as more degree leads to more complexity.Number of buffers and ports required increases with increase in the number of degree. Topologies like torus [5], folded torus [6] and mesh [7], have uniform degree routers and are easy to implement whereas Dmesh [8], diametricmesh [9], Tmesh [10], xmesh, xtorus and xxtorus [11] all have no uniform degree of routers. The new torus network which has the hypercube Q3 as the basic module has been proposed [12].…”

On an Overlaid Hybrid Wire/Wireless Interconnection Architecture for Network-on-chip

“…To overcome these problems, express virtual channels are introduced to various NoC architectures [2~6] that can improve NoC's power, latency and throughput performance [2]. However, as the interconnection wires in these schemes [2][3][4][5][6] are still metal, delays of these metallic interconnects, governed by the physical law of showing a quadratic relationship with respect to the wire length, and are still quite long even for a modest routing distance. Therefore, on-chip interconnects carrying signals across different components will be the bottleneck to system performance and reliability, especially when CMPs scale to hundreds or thousands of cores on a chip.…”