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In binary decision diagram-based fault tree analysis, the size of binary decision diagram encoding fault trees heavily depends on the chosen ordering. Heuristics are often used to obtain good orderings. The most important heuristics are depth-first leftmost (DFLM) and its variants weighting DFLM (WDFLM) and repeated-event-priority DFLM (RDFLM). Although having been used widely, their performance is still only vaguely understood, and not much formal work has been done. This article firstly identifies some basic requirements for a reliable benchmark and gives a benchmark generation method. Then, using the generated benchmark, the performance of DFLM and its variants is studied. Both the experimental results and some interesting findings for our research questions are proposed. This article also presents a new weighting DFLM (NWDFLM) heuristic and the underlying basic ideas and gives both the experimental results and conclusions on the performance comparison. As a final synthesis of all previous results, a practical suggestion of the order of heuristic selection to process a large fault tree is NWDFLM < WDFLM < RDFLM.

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Network on chip (NoC) is an effective solution to complex on-chip communication problem. The mesh topology is one of the most popular NoC. It has completely regular topology which can be implemented easily, but the communication delay between remote nodes is large. In this paper, we propose an improved topology called Tmesh, which is based on the standard mesh network by inserting four long links. We also present a deadlock-free routing algorithm for Tmesh named TXY algorithm. Indeed, our experimental results demonstrate a certain reduction in the average packet delay and routing hops. Keywords-mesh; routing algorithm; NoC I. INTRODUCTIONContinuous scaling of CMOS technology makes it possible to integrate a large number of cores on a chip multiprocessor (CMP) system. As a result, inter-core connection and communication becomes an important factor that affecting processor performance. Now there are three interconnection manners for CMP, which are bus, cross-switch and NoC [1][2][3][4][5]. When the number of cores is small, bus and cross-switch can satisfy the communication requirements. As the number of cores increasing, bus can not effectively deal with multiple data stream's concurrent transmission, and cross-switch causes exponential growth of hardware overhead. NoC becomes an effective solution to the interconnection of many cores.Compared with bus and cross-switch, NoC is based on macro computer network and has better reusability and scalability. At present, much research is based on mesh, torus topology, especially the mesh. Mesh is easy for physical implement and routing. It has been applied in practical design, such as Godson-3[5], TILE64 Processor [6]. However, it has large communication delay between remote nodes, increasing the possibility of network congestion [7]. Ogras proposed a method to optimize the performance of NoC [8], by inserting a few additional long-range links in mesh topology to reduce the communication delay between some nodes. This paper presents an improved mesh topology called Tmesh based on the above idea. We also give a routing algorithm named TXY algorithm. The experimental results demonstrate a certain reduction in the average packet delay and routing hops. When the network has 8×8 nodes, the average delay and routing hops of Tmesh are 2.92% and 3.53% lower than those of mesh respectively. This paper is organized as follows. In Section II, we describe Tmesh topology, and compare it with mesh from the network diameter, the ideal throughput and the ideal average delay. In Section III, present a routing algorithm for Tmesh and discuss the strategy of deadlock avoidance. In Section IV, the simulation environment and the performance analysis is given. Section V concludes the paper and indicates possible directions for future work.

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