An Improved SJ UMOS with Modified Gate Electrode to Reduce Gate Charge

Kushwaha, Prashant Kumar; Nautiyal, Payal; Gupta, Anshul; Naugarhiya, Alok; Verma, Shrish

doi:10.1109/iemeconx.2019.8877004

Cited by 3 publications

(2 citation statements)

References 13 publications

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“…Nonetheless, MOSFETs with SIPOS terminations have demonstrated resilience under harsh conditions, such as a gradient of 10 kV/μs. In Figure 9 b, a comparison of the R ON , sp and BV relationships is presented for the three structures, including references [ 2 , 3 , 17 , 21 , 22 , 23 , 24 , 25 ]. Optimum t OX , W N , L D , and N D values for SSJ-UMOS and S-UMOS are chosen for this analysis.…”

Section: Resultsmentioning

confidence: 99%

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Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET

Cao,

Sun,

et al. 2024

Micromachines

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This paper presents a machine learning-based figure of merit model for superjunction (SJ) U-MOSFET (SSJ-UMOS) with a modulated drift region utilizing semi-insulating poly-crystalline silicon (SIPOS) pillars. This SJ drift region modulation is achieved through SIPOS pillars beneath the trench gate, focusing on optimizing the tradeoff between breakdown voltage (BV) and specific ON-resistance (RON,sp). This analytical model considers the effects of electric field modulation, charge-coupling, and majority carrier accumulation due to additional SIPOS pillars. Gaussian process regression is employed for the figure of merit (FOM = BV2/RON,sp) prediction and hyperparameter optimization, ensuring a reasonable and accurate model. A methodology is devised to determine the optimal BV-RON,sp tradeoff, surpassing the SJ silicon limit. The paper also delves into a discussion of optimal structural parameters for drift region, oxide thickness, and electric field modulation coefficients within the analytical model. The validity of the proposed model is robustly confirmed through comprehensive verification against TCAD simulation results.

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Section: Resultsmentioning

confidence: 99%

“…In the ON state, the threshold voltage (V th ) signifies the initiation of the accumulation layer formation. Substituting ( 22) into (23), we obtain the integrated result for R A,sp as…”

Section: Figure Of Merit Bv-r Onsp Model For Ssj-umosmentioning

confidence: 99%

Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET

Cao,

Sun,

et al. 2024

Micromachines

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A deep trench super-junction LDMOS with double charge compensation layer

Wu¹,

Su²,

Chen³

et al. 2022

J. Semicond.

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A deep trench super-junction LDMOS with double charge compensation layer (DC DT SJ LDMOS) is proposed in this paper. Due to the capacitance effect of the deep trench which is known as silicon–insulator–silicon (SIS) capacitance, the charge balance in the super-junction region of the conventional deep trench SJ LDMOS (Con. DT SJ LDMOS) device will be broken, resulting in breakdown voltage (BV) of the device drops. DC DT SJ LDMOS solves the SIS capacitance effect by adding a vertical variable doped charge compensation layer and a triangular charge compensation layer inside the Con. DT SJ LDMOS device. Therefore, the drift region reaches an ideal charge balance state again. The electric field is optimized by double charge compensation and gate field plate so that the breakdown voltage of the proposed device is improved sharply, meanwhile the enlarged on-current region reduces its specific on-resistance. The simulation results show that compared with the Con. DT SJ LDMOS, the BV of the DC DT SJ LDMOS has been increased from 549.5 to 705.5 V, and the R on,sp decreased to 23.7 mΩ·cm2.

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Novel Accumulation Mode Superjunction Device With Extended Superjunction Gate

Chen

Zeng

et al. 2022

IEEE Trans. Electron Devices

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An Improved SJ UMOS with Modified Gate Electrode to Reduce Gate Charge

Cited by 3 publications

References 13 publications

Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET

Machine Learning-Based Figure of Merit Model of SIPOS Modulated Drift Region for U-MOSFET

A deep trench super-junction LDMOS with double charge compensation layer

Novel Accumulation Mode Superjunction Device With Extended Superjunction Gate

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