An improvement in the restoring division algorithm (Needy Restoring Division Algorithm)

Aggarwal, Nitish; Asooja, Kartik; Verma, Saurabh Shekhar; Negi, Sapna

doi:10.1109/iccsit.2009.5234956

Cited by 16 publications

(13 citation statements)

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“…To increase the computation speed with minimized hardware the Vedic mathematics [6]multiplication principle is used. These architectures are used to improve the speed of the RSA algorithm with reduced hardware [7], [8].…”

Section: B Vedic Implementationmentioning

confidence: 99%

Improved Mask Protected DES using RSA Algorithm

Latha

Sivabalan

2016

MATEC Web of Conferences

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The data encryption standard is a pioneering and farsighted standard which helped to set a new paradigm for encryption standards. But now DES is considered to be insecure for some application. Asymmetric mask protected DES is an advanced encryption method for effectively protecting the advanced DES. There are still probabilities to improve its security. This paper propose a method, which introduce a RSA key generation scheme in mask protected DES instead of plain key, which result in enhancement in the security of present asymmetric mask protected DES. We further propose a Vedic mathematical method of RSA implementation which reduce the complexity of computation in RSA block thereby resulting in reduced delay (four times)that improves the performance of overall system. The software implementation was performed using Xilinx 13.2 and Model-Sim was used for the simulation environment.

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Section: B Vedic Implementationmentioning

confidence: 99%

Improved Mask Protected DES using RSA Algorithm

Latha

Sivabalan

2016

MATEC Web of Conferences

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“…An improvement in the current restoring computer division algorithm [11] which minimizes the number of restorations performed by the computer. Currently, restoration is checked after each shifting of the register but deprived Restoring Division Algorithm checks restoration only when it is needed.…”

Section: Backgrund and Related Wrkmentioning

confidence: 99%

A Novel Vedic Divider Architecture with Reduced Delay for VLSI Applications

Panda¹,

Sahu²

2015

IJCA

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The ever increasing demand in VLSI architecture to handle complex systems has resulted for designing of high speed divider architecture. The divider is designed using ever known ancient methodology "Vedic mathematics". There are several methods present in Vedic mathematics but here Parvartya sutra is used. It is a general division formula which can be applicable to all cases of division which is an efficient way for dividing large numbers with respect to delay and power consumption. Here thirty-two bit divider architecture is implemented using this sutra & synthesized and simulated using Xilinx ISE simulator and implemented on virtex4 FPGA device XC4VLX15.The output parameters such as propagation delay and device utilization are calculated from synthesis results. Our result shows speed improvement as compared to other architecture presented in this literature. This architecture can be implemented in many applications such as digital signal processing, cryptography, processor arithmetic unit design etc.

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“…Division is a fundamental operation in many scientific and engineering applications, like scientific arithmetic computation, signal processing, rendering systems, artificial intelligence, graphics compression etc [6][7][8][9]. Inherently, division operations are sequential type of operation; thereby it is more costly in terms of propagation delay compared to other mathematical operations like addition, subtraction and multiplication [7][8][9][10]. In general, the division architecture can be classified into two categories: iterative like digit recurrence [11,12] and multiplication based like functional iteration (Newton-Raphson method [13,14]).…”

Section: Introductionmentioning

confidence: 99%

Integer division technique for signal processing applications

Kumar

Sharma

Saha

2015

Proceedings of the 9th International Conference on Ubiquitous Information Management and Communication

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Algorithmic implementation of integer division technique based on ancient Vedic mathematics is reported in this paper. The potentiality of the 'Nikhilam Navatascaramam Dasatah (NND)' (all from 9 and last from 10)' sutra of Vedic mathematics was adopted to implement the high speed integer division. Optimized 4221 BCD encoding technique was incorporated with Vedic mathematics, to implement such divider for practical signal processing applications. Propagation delay and dynamic switching power consumption of division circuitry were minimized significantly through stage reduction techniques of such sutra (formulae). The functionality of the division circuitry was checked and performance parameters like propagation delay and dynamic power consumption were calculated by Xilinx tool (VHDL language). The propagation delay of the resulting 6÷3 digit divisor circuitry was only ~41ns and consumed ~93mW power. Amalgam-nation of BCD arithmetic with ancient Vedic mathematics, substantial amount of iterations were eliminated owing to ~20% reduction in delay and ~12% reduction in power from its counterpart.

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An improvement in the restoring division algorithm (Needy Restoring Division Algorithm)

Cited by 16 publications

References 0 publications

Improved Mask Protected DES using RSA Algorithm

Improved Mask Protected DES using RSA Algorithm

A Novel Vedic Divider Architecture with Reduced Delay for VLSI Applications

Integer division technique for signal processing applications

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