An in-depth analysis of temperature effect on DIBL in UTBB FD SOI MOSFETs based on experimental data, numerical simulations and analytical models

Pereira, A. S. N.; Streel, Guerric de; Planes, N.; Haond, M.; Giacomini, Renato; Flandre, Denis; Kilchytska, Valeriya

doi:10.1016/j.sse.2016.10.017

Cited by 2 publications

(2 citation statements)

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“…However, (2) retains the clear physical meaning and becomes the simplification of (1) to help us analytically derive the B-S potential coupling relation. We integrated (2) twice to obtain this relation as:…”

Section: Surface Potential Explicit Calculation Schemementioning

confidence: 99%

“…Silicon integrated circuits (ICs) have become increasingly dense because the feature size of MOSFETs based on silicon-on-insulator (SOI) structure has not been a constraint in the sub-nanometer scale and both performance and cost improve as the feature size decreases. Up to now, there has still been considerable interest in optimizing properties of SOI MOSFETs [1][2][3] due to the widespread applications of SOI MOSFETs, such as sensors [4], memories [5], millimeter-wave circuits [6], and so on. Therefore, both device property optimization and IC design in the different fields imply that an analytical I-V model for accurately predicting I-V characteristics of SOI MOSFETs is imperative.…”

Section: Introductionmentioning

confidence: 99%

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A Surface-Potential-Based Analytical I-V Model of Full-Depletion Single-Gate SOI MOSFETs

Huang

et al. 2019

Electronics

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A surface-potential-based analytical I-V model of single-gate (SG) silicon-on-insulator (SOI) MOSFETs in full-depletion (FD) mode is proposed and compared with numerical data and Khandelwal's experimental results. An explicit calculation scheme of surface potential, processing high computation accuracy and efficiency, is demonstrated according to the derivation of the coupling relation between surface potential and back-channel potential. The maximum absolute error decreases into 10 −7 V scale, and computation efficiency is improved substantially compared with numerical iteration. Depending on the surface potential, the drain current is derived in closed-form and validated by Khandelwal's experimental data. High computation accuracy and efficiency suggest that this analytical I-V model displays great promise for SOI device optimizations and circuit simulations.

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Section: Surface Potential Explicit Calculation Schemementioning

confidence: 99%