An In-depth Study of High-Performing Strained Germanium Nanowires pFETs

Mitard, J.; Jang, Doyoung; Eneman, G.; Arimura, Hiroaki; Parvais, B.; Richard, Olivier; Marcke, P. Van; Witters, L.; Capogreco, E.; Bender, Hugo; Ritzenthaler, R.; Mertens, Hans; Hikavyy, Andriy; Loo, Roger; Dekkers, Harold; Sebaai, Farid; Milenin, Alexey; Horiguchi, N.; Mocuta, A.; Mocuta, D.; Collaert, N.

doi:10.1109/vlsit.2018.8510666

Cited by 11 publications

(3 citation statements)

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“…Two types of multilayer epistructures, which are Si 0.8 Ge 0.2 (40 nm)/Ge(40 nm) (referred to as Structure A) and Si 0.8 Ge 0.2 (40 nm)/Ge(40 nm)/Si 0.8 Ge 0.2 (40 nm)/Ge(40 nm)/Si(40 nm)/Ge(40 nm) (referred to as Structure B), were grown on SOI substrates for device fabrication and characterization. The sandwiched-Ge layer was adopted as sacrificial interlayers between Si or Si 0.8 Ge 0.2 because of the extremely high etching selectivity of Ge over Si and Si 0.8 Ge 0.2 − when H 2 O 2 solution was utilized for Ge removal. This selective etch process facilitates the formation of suspending Si or Si 0.8 Ge 0.2 NS (nanosheet) and the subsequent isolation process between the top Si 0.8 Ge 0.2 and bottom Si channels.…”

Section: Device Fabricationmentioning

confidence: 99%

Fabrication of CFETs with Vertically Stacked p-SiGe/n-Si Channels by SiGe/Ge/Si Multilayer Epitaxy and Ge Selective Etching

Chu,

Chen,

Chang

et al. 2024

ACS Appl. Electron. Mater.

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This study presents a straightforward approach for fabricating heterogeneous complementary FET (CFET) devices. The process flow commences with a SiGe/Ge/Si epitaxial multilayer structure grown on a SOI substrate. The source/drains for both stacked devices were straightforwardly performed through P and B implantations with precise depth control, respectively. The isolation of the top p-SiGe FET from the bottom n-Si FET was achieved by etching away the middle Ge sacrificial layer and subsequently filled with SiO2 dielectric material. The etching selectivity of Ge over Si and Si0.8Ge0.2 by utilizing a H2O2 solution was nearly infinite, resulting in a flawless structure with p-SiGe channels stacked over n-Si channels. Finally, a functional CFET inverter device composed of a top inversion mode (IM) SiGe nanosheet pFET and a bottom IM Si nanosheet nFET was demonstrated.

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Section: Device Fabricationmentioning

confidence: 99%

Fabrication of CFETs with Vertically Stacked p-SiGe/n-Si Channels by SiGe/Ge/Si Multilayer Epitaxy and Ge Selective Etching

Chu,

Chen,

Chang

et al. 2024

ACS Appl. Electron. Mater.

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“…Moreover, the high interface trap density (D it ) at the channel/dielectric interface caused by the undesired formation of GeO x in the interfacial layers [5,6] leads to poor subthreshold behaviors. Recently, the state-of-the-art stacked Si channel GAAFETs [7] and the stacked Ge channel GAAFETs [8][9][10] have been reported. The stacked Si channel GAAFETs have good subthreshold slope (SS) under 70 mV/dec even with sub-30 nm gate length [7].…”

Section: Introductionmentioning

confidence: 99%

Novel vertically stacked Ge_0.85Si_0.15nGAAFETs above a Si channel with low SS of 76 mV/dec by underneath Si channel and enhancedI_on(1.7X atV_OV=V_DS= 0.5 V) by Ge_0.85Si_0.15channels

Liu¹,

Huang²,

Lu³

et al. 2020

Semicond. Sci. Technol.

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An engineering solution is provided to improve the electrostatic behaviors of Ge-based channels gate-all-around FETs. We demonstrate the vertically stacked Ge 0.85 Si 0.15 channels above a Si channel, which has good subthreshold behaviors. The two Ge 0.85 Si 0.15 channels are tensily strained to improve I on . With optimized channel dimensions, the threshold voltage of Ge 0.85 Si 0.15 channels is more positive than the Si channel by quantum confinement. Therefore, the underneath Si channel with good electrostatic control dominates the subthreshold region. Good subthreshold slope=76 mV/dec and low drain-induced barrier lowering=36 mV/V are achieved. For on-state, the stacked high-mobility GeSi channels turn on after the Si channel to achieve I on of 13.9 μA per stack at V OV =V DS =0.5 V.

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“…As complementary metal−oxide−semiconductor technology continues to scale to 5 nm and beyond, SiGe or Ge high mobility channels have been introduced 1,2 and fin field effect transistor (FinFET) technology by a gate-all-around (GAA) architecture. 3 Although the lower bandgap of Ge compared with that of Si imposes a limitation on the achievable off-state current, Ge GAA devices can mitigate offstate leakage owing to bandgap broadening, which is induced by quantum confinement effects.…”

mentioning

confidence: 99%

Key Process Technologies for Stacked Double Si_0.7Ge_0.3 Channel Nanowires Fabrication

Li¹,

Cheng²,

Zhong³

et al. 2020

ECS J. Solid State Sci. Technol.

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In this study, key process technologies, such as epitaxy growth, fin structure etching, and selective etching of stacked Si/SiGe multilayer for the fabrication of double Si 0.7 Ge 0.3 channel nanowires under a reasonable thermal budget are systematically investigated. A high crystal quality two-period Si 0.7 Ge 0.3 /Si stacked multilayer epitaxially grown with thin and distinct interfaces is first realized on a Si substrate. A vertical profile of the fin structure of Si 0.7 Ge 0.3 /Si stacked multilayer is achieved using HBr/O 2 /He plasma after fine-tuning the etching process. In addition, the highest tolerable temperature of 850 °C for the Si 0.7 Ge 0.3 /Si stacked multilayer under rapid thermal annealing is confirmed based on the crystal quality, Si 0.7 Ge 0.3 /Si interface, and Ge diffusion. Moreover, a rectangular Si 0.7 Ge 0.3 extremity profile is realized by optimizing the concentration and temperature of tetramethyl ammonium hydroxide solution to achieve selective etching of Si to Si 0.7 Ge 0.3 for Si 0.7 Ge 0.3 /Si stacked multilayers. Finally, a vertically stacked double Si 0.7 Ge 0.3 nanowire structure is successfully prepared using these newly developed process technologies.

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An In-depth Study of High-Performing Strained Germanium Nanowires pFETs

Cited by 11 publications

References 0 publications

Fabrication of CFETs with Vertically Stacked p-SiGe/n-Si Channels by SiGe/Ge/Si Multilayer Epitaxy and Ge Selective Etching

Fabrication of CFETs with Vertically Stacked p-SiGe/n-Si Channels by SiGe/Ge/Si Multilayer Epitaxy and Ge Selective Etching

Novel vertically stacked Ge_0.85Si_0.15nGAAFETs above a Si channel with low SS of 76 mV/dec by underneath Si channel and enhancedI_on(1.7X atV_OV=V_DS= 0.5 V) by Ge_0.85Si_0.15channels

Key Process Technologies for Stacked Double Si_0.7Ge_0.3 Channel Nanowires Fabrication

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An In-depth Study of High-Performing Strained Germanium Nanowires pFETs

Cited by 11 publications

References 0 publications

Fabrication of CFETs with Vertically Stacked p-SiGe/n-Si Channels by SiGe/Ge/Si Multilayer Epitaxy and Ge Selective Etching

Fabrication of CFETs with Vertically Stacked p-SiGe/n-Si Channels by SiGe/Ge/Si Multilayer Epitaxy and Ge Selective Etching

Novel vertically stacked Ge0.85Si0.15nGAAFETs above a Si channel with low SS of 76 mV/dec by underneath Si channel and enhancedIon(1.7X atVOV=VDS= 0.5 V) by Ge0.85Si0.15channels

Key Process Technologies for Stacked Double Si0.7Ge0.3 Channel Nanowires Fabrication

Contact Info

Product

Resources

About

Novel vertically stacked Ge_0.85Si_0.15nGAAFETs above a Si channel with low SS of 76 mV/dec by underneath Si channel and enhancedI_on(1.7X atV_OV=V_DS= 0.5 V) by Ge_0.85Si_0.15channels

Key Process Technologies for Stacked Double Si_0.7Ge_0.3 Channel Nanowires Fabrication