Key Process Technologies for Stacked Double Si_0.7Ge_0.3 Channel Nanowires Fabrication

Abstract

In this study, key process technologies, such as epitaxy growth, fin structure etching, and selective etching of stacked Si/SiGe multilayer for the fabrication of double Si 0.7 Ge 0.3 channel nanowires under a reasonable thermal budget are systematically investigated. A high crystal quality two-period Si 0.7 Ge 0.3 /Si stacked multilayer epitaxially grown with thin and distinct interfaces is first realized on a Si substrate. A vertical profile of the fin structure of Si 0.7 Ge 0.3 /Si stacked multilayer is achieved using HBr/O 2 /He plasma after fine-tuning the etching process. In addition, the highest tolerable temperature of 850 °C for the Si 0.7 Ge 0.3 /Si stacked multilayer under rapid thermal annealing is confirmed based on the crystal quality, Si 0.7 Ge 0.3 /Si interface, and Ge diffusion. Moreover, a rectangular Si 0.7 Ge 0.3 extremity profile is realized by optimizing the concentration and temperature of tetramethyl ammonium hydroxide solution to achieve selective etching of Si to Si 0.7 Ge 0.3 for Si 0.7 Ge 0.3 /Si stacked multilayers. Finally, a vertically stacked double Si 0.7 Ge 0.3 nanowire structure is successfully prepared using these newly developed process technologies.

Four-Period Vertically Stacked SiGe/Si Channel FinFET Fabrication and Its Electrical Characteristics

“…Then, the vertical Fin pattern with stacked SiGe/Si multilayer on the top of Si substrate were formed by a spacer image transfer (SIT) technique under an optimal HBr/O 2 /He plasma. After STI filling and planarization, a low temperature of 850 °C for 30 s STI densification anneal and 1:100 diluted HF solution Fin reveal was implemented to attain a stacked SiGe/Si Fin formation [ 16 ]. Then, a low temperature SiO 2 deposition and dummy gate patterning were performed.…”

“…After spacer 1 and spacer 2 definition, lightly doped drain (LDD) and source and drain (S/D) implantation was implemented with B and BF 2 dopant respectively. A low temperature dopant activation of 850 °C for 30 s was performed to keep the stacked SiGe/Si Fin stability [ 16 ]. Inter layer dielectric (ILD) deposition and CMP was employed to exposure the dummy gate.…”

“…filling and planarization, a low temperature of 850 °C for 30 s STI densification anneal and 1:100 diluted HF solution Fin reveal was implemented to attain a stacked SiGe/Si Fin formation [16]. Then, a low temperature SiO2 deposition and dummy gate patterning were performed.…”

Advanced process and electron device technology

“…For Si-based channel devices, in-situ B-doping in SiGe is considered to be the best option for the S/D stressor. Typical SiGe epitaxy process temperatures are approximately 650 ˚C with conventional precursors (SiH 4 , DCS, and GeH 4 / to have high growth rates [77][78][79] . HCl is used to obtain the selective epitaxy growth of SiGe in exposed source and drain areas without unwanted amorphous or polycrystalline SiGe deposition on oxides and nitrides.…”

4-Levels Vertically Stacked SiGe Channel Nanowires Gate-All-Around Transistor with Novel Channel Releasing and Source and Drain Silicide Process

“…Among them, SiGe materials, especially those with Ge concentration between 20% and 40%, have been considered as the channel material of GAA devices. This is because they have higher electron and hole mobility, better negative bias temperature instability (NBTI) reliability [ 8 , 9 ] than Si and are more compatible with present Si platform [ 9 , 10 , 11 ]. However, the fabrication of stacked SiGe nanowire/nanosheet (NW/NS) GAA devices still face many challenges, such as a high-quality stacked SiGe/Si fin structure preparation, high selectively SiGe NW/NS release, inner spacer, source/drain (S/D) epitaxial process, etc.…”