An inductor modeling and optimization toolbox for RF circuit design

Passos, Fábio; Roca, E.; Castro-López, R.; Fernández, Francisco V.

doi:10.1016/j.vlsi.2017.01.009

Cited by 15 publications

(5 citation statements)

References 14 publications

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“…Hence, we use a state-ofthe-art ML technique to model inductors [28]. It is a MATLAB toolbox (SIDe-O), which allows the designer to perform inductor design and optimization within milliseconds [29]. The model achieves less than 1% error compared to EM simulations and does not impact the accuracy of the inductor design.…”

Section: B Lowest Hierarchy Level: Passive Devicesmentioning

confidence: 99%

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Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

et al. 2021

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This paper presents an innovative yield-aware synthesis strategy based on a hierarchical bottom-up methodology that uses a multiobjective evolutionary optimization algorithm to design a complete radiofrequency integrated circuit from the passive component level up to the system level. Within it, performances' calculation aims for the highest possible accuracy. A surrogate model calculates the performances for the inductive devices, with accuracy comparable to full electromagnetic simulation; and, an electrical simulator calculates circuit-and system-level performances. Yield is calculated using Monte-Carlo (MC) analysis with the foundry-provided models without any model approximation. The computation of the circuit yield throughout the hierarchy is estimated employing parallelism and reducing the number of simulations by performing MC analysis only to a reduced number of candidate solutions, alleviating the computational requirements during the optimization. The yield of the elements not accurately evaluated is assigned using their degree of similitude to the simulated solutions. The result is a novel synthesis methodology that reduces the total optimization time compared to a complete MC yield-aware optimization. Ultimately, the methodology proposed in this work is compared against other methodologies that do not consider yield throughout the system's complete hierarchy, demonstrating that it is necessary to consider it over the entire hierarchy to achieve robust optimal designs.

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Section: B Lowest Hierarchy Level: Passive Devicesmentioning

confidence: 99%

“…The model achieves less than 1% error compared to EM simulations and does not impact the accuracy of the inductor design. We follow the approach in [29], and the passive component design is considered an additional level of the hierarchy.…”

Section: B Lowest Hierarchy Level: Passive Devicesmentioning

confidence: 99%

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

et al. 2021

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“…3(a), using the geometric parameters of the data samples, i.e., inner diameter, number of turns and turn width, are performed. Afterwards, the EM simulation results are used to train the surrogate structure that models the complete inductor search space using the setup proposed in [31], and illustrated in Fig. 2(a).…”

Section: A Integrated Inductor Designmentioning

confidence: 99%

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop

Martins

Lourenço

Passos

et al. 2019

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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In this paper, an analysis of the methodologies proposed in the past years to automate the synthesis of radiofrequency (RF) integrated circuit blocks is presented. In the light of this analysis, and to avoid non-systematic iterations between sizing and layout design steps, a multi-objective optimizationbased layout-aware sizing approach with pre-optimized integrated inductor(s) design space is proposed. An automatic layout generation from netlist to ready-to-fabricate prototype is carried in-the-loop for each tentative sizing solution using an RFspecific module generator, template-based placer and evolutionary multi-net router with pre-optimized interconnect widths. The proposed approach exploits the full capabilities of the most established computer-aided design tools for RF design available nowadays, i.e., RF circuit simulator as performance evaluator, electromagnetic simulator for inductor characterization, and layout extractor to determine the complete circuit layout parasitics. Experiments are conducted over a widely-used circuit in the RF context, showing the advantages of performing complete layout-aware sizing optimization from the very initial stages of the design process.

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“…In this work, the accuracy and efficiency of surrogate modeling approaches is exploited. Therefore, in order to generate the inductor POF, SIDe-O is used [13]. This toolbox is based on surrogate models that allow an accurate characterization with less than 1% error when compared with EM simulations [14].…”

Section: Inductor Pof Generationmentioning

confidence: 99%

Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology

et al. 2018

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In this paper a design strategy based on bottomup design methodologies is used in order to systematically design a voltage controlled oscillator. The methodology uses two computer-aided design tools: AIDA, a multi-objective multiconstraint circuit optimization tool, and SIDe-O, a tool that characterizes and optimizes integrated inductors with high accuracy (around 1% when compared to electromagnetic simulations). By using such tools, the difficult trade-offs inherent to radio-frequency circuits can be explored efficiently and accurately. Furthermore, with the capability that AIDA has at considering process parameter variations during the optimization, the resulting methodology is able to obtain truly robust circuit designs.

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An inductor modeling and optimization toolbox for RF circuit design

Cited by 15 publications

References 14 publications

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

Hierarchical Yield-Aware Synthesis Methodology Covering Device-, Circuit-, and System-Level for Radiofrequency ICs

Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop

Enhanced systematic design of a voltage controlled oscillator using a two-step optimization methodology

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