An industrially effective environment for formal hardware verification

Seger, C.-J.H.; Jones, Robert B.; O’Leary, John; Melham, Tom; Aagaard, Mark; Barrett, Clark; Syme, Don

doi:10.1109/tcad.2005.850814

Cited by 74 publications

(69 citation statements)

References 60 publications

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“…Our method has been implemented in reFLect, the lazy functional language used to program Intel's Forte tool suite [14], and sits as a specification layer on top of the Relational STE [10] symbolic simulator. The design under verification was from a next-generation many-core CPU under development at Intel R .…”

Section: Case Studiesmentioning

confidence: 99%

Verifying Relative Error Bounds Using Symbolic Simulation

Bingham

Leslie-Hurd

2014

Computer Aided Verification

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Abstract. In this paper we consider the problem of formally verifying hardware that is specified to compute reciprocal, reciprocal square root, and power-of-two functions on floating point numbers to within a given relative error. Such specifications differ from the common case in which any given input is specified to have exactly one correct output. Our approach is based on symbolic simulation with binary decision diagrams, and involves two distinct steps. First, we prove a lemma that reduces the relative error specification to several inequalities that involve reasoning about natural numbers only. The most complex of these inequalities asserts that the product of several naturals is less-than/greaterthan another natural. Second, we invoke one of several customized algorithms that decides the inequality, without performing the expensive symbolic multiplications directly. We demonstrate the effectiveness of our approach on a next-generation Intel R processor design and report encouraging time and space metrics for these proofs.

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Section: Case Studiesmentioning

confidence: 99%

Verifying Relative Error Bounds Using Symbolic Simulation

Bingham

Leslie-Hurd

2014

Computer Aided Verification

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“…STE's combination of abstraction and algorithmic efficiency is especially suited to verification of datapaths and memories, and has been demonstrated on many hard industrial verification problems [2], [3], [4]. A notable success is the verification, using Intel's Forte system [5], of the entire execution cluster of the Intel Core 2 Duo and Core i7 microprocessors [6], [7] As with most property verification, STE correctness results are usually conditional on various assumptions about the hardware environment within which the verified block is operating. Assumptions are made about how the inputs to the verified block are driven.…”

Section: Introductionmentioning

confidence: 99%

Assume-guarantee validation for STE properties within an SVA environment

Khasidashvili

Gavrielov

Melham

2009

2009 Formal Methods in Computer-Aided Design

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Abstract-Symbolic Trajectory Evaluation is an industrialstrength verification method, based on symbolic simulation and abstraction, that has been highly successful in data path verification, especially microprocessor execution units. These correctness results are typically obtained under certain assumptions about how the verified hardware block's inputs are driven, as well as assumptions about the values of these inputs. For correct overall operation, the hardware environment within which the verified block resides is expected to satisfy these assumptions.We describe a translation of these proof assumptions into System Verilog Assertions. These are then used as checkers in dynamic validation of the hardware environment within which blocks verified by Symbolic Trajectory Evaluation operate. The result is a pragmatic assume-guarantee method that increases the quality and confidence in verification results, requires little or no modification to the Symbolic Trajectory Evaluation proofs, and leverages pre-existing dynamic validation infrastructure.

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“…For evaluating our algorithm RespST E, presented in Section 4, we implemented and used it in conjunction with Forte, a BDD based STE tool by Intel [14].…”

Section: Resultsmentioning

confidence: 99%

“…In order to evaluate our algorithm RespST E, we implemented it and used it in conjunction with Forte, a BDD based STE tool by Intel [14]. We applied it to several circuits and specifications.…”

Section: Introductionmentioning

confidence: 99%

Efficient Automatic STE Refinement Using Responsibility

Chockler

Grumberg

Yadgar

Tools and Algorithms for the Construction and Analysis of Systems

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Abstract. Symbolic Trajectory Evaluation (STE) is a powerful technique for hardware model checking. It is based on 3-valued symbolic simulation, using 0,1, and X ("unknown"). X is used to abstract away values of circuit nodes, thus reducing memory and runtime of STE runs. The abstraction is derived from a given user specification.An STE run results in "pass" (1), if the circuit satisfies the specification, "fail" (0) if the circuit falsifies it, and "unknown" (X), if the abstraction is too coarse to determine either of the two. In the latter case, refinement is needed: The X values of some of the abstracted inputs should be replaced. The main difficulty is to choose an appropriate subset of these inputs that will help to eliminate the "unknown" STE result, while avoiding an unnecessary increase in memory and runtime. The common approach to this problem is to manually choose these inputs.This work suggests a novel approach to automatic refinement for STE, which is based on the notion of responsibility. For each input with X value we compute its Degree of Responsibility (DoR) to the "unknown" STE result. We then refine those inputs whose DoR is maximal.We implemented an efficient algorithm, which is linear in the size of the circuit, for computing the approximate DoR of inputs. We used it for refinements for STE on several circuits and specifications. Our experimental results show that DoR is a very useful device for choosing inputs for refinement. In comparison with previous works on automatic refinement, our computation of the refinement set is faster, STE needs fewer refinement iterations and uses less overall memory and time.

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An industrially effective environment for formal hardware verification

Abstract: NoticeThis material is presented to ensure timely dissemination of scholarly and technical work.

Cited by 74 publications

References 60 publications

Verifying Relative Error Bounds Using Symbolic Simulation

Verifying Relative Error Bounds Using Symbolic Simulation

Assume-guarantee validation for STE properties within an SVA environment

Efficient Automatic STE Refinement Using Responsibility

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