NoticeThis material is presented to ensure timely dissemination of scholarly and technical work.

Symbolic trajectory evaluation is a new approach to formal hardware verification combining the circuit modeling capabilities of symbolic logic simulation with some of the analytic methods found in temporal logic model checkers. We have created such an evaluator by extending the symbolic switch-level simulator COSMOS. This program gains added efficiency by exploiting the ability of COSMOS to evaluate circuit operation over a ternary logic model, where the third value X represents an unknown logic value. This program can formally verify systems containing complex featurea such as switch-level models, detailed timing, and pipelining.

NoticeThis material is presented to ensure timely dissemination of scholarly and technical work.

Abstract

Formalhardware veri cation based on symbolic trajectory evaluation shows considerable promise in verifying medium to large scale VLSI designs with a high degree of automation. However, in order to verify today's designs, a method for composing partial veri cation results is needed. One way of accomplishing this is to use a general purpose theorem prover to combine the verication results obtained by other tools. However, a specialised purpose theorem prover is more attractive since it can more easily exploit symbolic trajectory evaluation (and may be easier to use). Consequently we explore the possibility of developing a much simpler, but more tailor made, theorem prover designed speci cally for combining veri cation results based on trajectory evaluation. In the paper we discuss the underlying inference rules of the prover as well as more practical issues regarding the user interface. We nally conclude with a couple of examples in which we are able to verify designs that could not have been veri ed directly. In particular, the complete veri cation of a 64 bit multiplier takes approximately 15 minutes on a Sparc 10 machine.