The formal verification of a pipelined double-precision IEEE floating-point multiplier

Aagaard, Mark; Seger, C.-J.H.

doi:10.1109/iccad.1995.479878

Cited by 32 publications

(24 citation statements)

References 7 publications

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“…In [16], [17] a combination of theorem proving and symbolic trajectory evaluation [18] is used to verify multiplier designs. Both approaches decompose the general proof into several proof steps.…”

Section: Previous Workmentioning

confidence: 99%

Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof

Krautz

Wedler

Kunz

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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In this paper we describe a practical methodology to formally verify highly optimized, industrial multipliers. We define a multiplier description language which abstracts from low-level optimizations and which can model a wide range of common implementations at a structural and arithmetic level. The correctness of the created model is established by bit level transformations matching the model against a standard multiplication specification. The model is also translated into a gate netlist to be compared with the full-custom implementation of the multiplier by standard equivalence checking. The advantage of this approach is that we use a high level language to provide the correlation between structure and bit level arithmetic. This compares favorably with other approaches that have to spend considerable effort on extracting this information from highly optimized implementations. Our approach is easily portable and proved applicable to a wide variety of state-of-the-art industrial designs.

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Section: Previous Workmentioning

confidence: 99%

Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof

Krautz

Wedler

Kunz

et al. 2008

2008 Asia and South Pacific Design Automation Conference

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show abstract

“…Claesen et al 98 used theorem proving to formally verify an SRT integer divider. Aagaard and Seger 99 combined model checking and theorem proving to show the correctness of an Intel multiplier. O'Leary et al 100 formally verified an SRT integer square root circuit.…”

Section: Related Workmentioning

confidence: 99%

Integrating Formal Verification into an Advanced Computer Architecture Course

Velev

2005

IEEE Trans. Educ.

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Abstract. The paper presents a sequence of three projects on design and formal verification of pipelined and superscalar processors. The projects were integrated-by means of lectures and preparatory homework exercises-into an existing advanced computer architecture course taught to both undergraduate and graduate students in a way that required them to have no prior knowledge of formal methods. The first project was on design and formal verification of a 5-stage pipelined DLX processor, implementing the six basic instruction types-register-register-ALU, registerimmediate-ALU, store, load, jump, and branch. The second project was on extending the processor from project one with ALU exceptions, a return-from-exception instruction, and branch prediction; each of the resulting models was formally verified. The third project was on design and formal verification of a dual-issue superscalar version of the DLX from project one. The preparatory homework problems included an exercise on design and formal verification of a staggered ALU, pipelined in the style of the integer ALUs in the Intel Pentium 4. The processors were described in the high-level hardware description language AbsHDL that allows the students to ignore the bit widths of word-level values and the internal implementations of functional units and memories, while focusing entirely on the logic that controls the pipelined or superscalar execution. The formal verification tool flow included the term-level symbolic simulator TLSim, the decision procedure EVC, and an efficient SAT-checker; this tool flow-combined with the same abstraction techniques for defining processors with exceptions and branch prediction, as used in the projects-was applied at Motorola to formally verify a model of the M•CORE processor, and detected bugs. The course went through two iterations-offered at the Georgia Institute of Technology in the summer and fall of 2002-and was taught to 67 students, 25 of whom were undergraduates.

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“…Aagaard and Seger [1] combined BDD-based model-checking and theorem proving techniques in the Voss hardware verification system to verify the IEEE compliance of the gate-level implementation of a floating-point multiplier. O'Leary et al [34] reported on the specification and verification of the Intel Pentium R Pro processor's floating-point execution unit at the gate level using a combination of model-checking and theorem proving.…”

Section: Related Workmentioning

confidence: 99%

“…where v n represents the n th bit of the binary string in the fixed-point number, 1 and M and N are respectively fracbits and wordlength. In HOL, we define the valuation function value that returns the corresponding real value of a fixed-point number.…”

Section: Fixed-point Valuationmentioning

confidence: 99%

Formalization of Fixed-Point Arithmetic in HOL

Akbarpour

Tahar

Dekdouk

2005

Form Method Syst Des

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Abstract. This paper addresses the formalization in higher-order logic of fixed-point arithmetic. We encoded the fixed-point number system and specified the different quantization modes in fixed-point arithmetic such as the directed and even quantization modes. We also considered the formalization of exceptions detection and their handling like overflow and invalid operation. An error analysis is then performed to check the correctness of the quantized result after carrying out basic arithmetic operations, such as addition, subtraction, multiplication and division against their mathematical counterparts. Finally, we showed by an example how this formalization can be used to enable the verification of the transition from floating-point to fixed-point algorithmic level in the signal processing design flow.

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The formal verification of a pipelined double-precision IEEE floating-point multiplier

Abstract: Abstract

Cited by 32 publications

References 7 publications

Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof

Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof

Integrating Formal Verification into an Advanced Computer Architecture Course

Formalization of Fixed-Point Arithmetic in HOL

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