Verifying full-custom multipliers by Boolean equivalence checking and an arithmetic bit level proof

Abstract

In this paper we describe a practical methodology to formally verify highly optimized, industrial multipliers. We define a multiplier description language which abstracts from low-level optimizations and which can model a wide range of common implementations at a structural and arithmetic level. The correctness of the created model is established by bit level transformations matching the model against a standard multiplication specification. The model is also translated into a gate netlist to be compared with the full-custom implementation of the multiplier by standard equivalence checking. The advantage of this approach is that we use a high level language to provide the correlation between structure and bit level arithmetic. This compares favorably with other approaches that have to spend considerable effort on extracting this information from highly optimized implementations. Our approach is easily portable and proved applicable to a wide variety of state-of-the-art industrial designs.

A Theoretical Framework for Symbolic Quick Error Detection

“…In a formal approach, a property corresponding to Spec op (based on the ISA) is written for each opcode op ∈ Op, and the model checker is used to ensure that the property holds when starting from any initial state. Because the approach is restricted to initial states and only a single instruction execution, it is much simpler to specify and check than would be a property specifying the full correctness of P. Efficient specialized approaches exist for checking multiplier units [31]- [34], which is computationally hard.…”