Modeling of custom-designed arithmetic components for ABL normalization

Pavlenko, E. Yu.; Wedler, Markus; Stoffel, Dominik; Kunz, Wolfgang; Wienand, Oliver; Karibaev, Evgeny

doi:10.1109/fdl.2008.4641433

Cited by 7 publications

(3 citation statements)

References 10 publications

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“…Approaches based on bit-level reverse engineering [86,95] use arithmetic bit-level representations, which are extracted from the given gate-level netlists. This technique is able to verify simple multipliers, but fails to verify non-trivial multiplier architectures.…”

Section: Eidesstattliche Erklärungmentioning

confidence: 99%

Formal verification of multiplier circuits using computer algebra

Kaufmann

2022

It - Information Technology

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Digital circuits are widely utilized in computers, because they provide models for various digital components and arithmetic operations. Arithmetic circuits are a subclass of digital circuits that are used to execute Boolean algebra. To avoid problems like the infamous Pentium FDIV bug, it is critical to ensure that arithmetic circuits are correct. Formal verification can be used to determine the correctness of a circuit with respect to a certain specification. However, arithmetic circuits, particularly integer multipliers, represent a challenge to current verification methodologies and, in reality, still necessitate a significant amount of manual labor. In my dissertation we examine and develop automated reasoning approaches based on computer algebra, where the word-level specification, modeled as a polynomial, is reduced by a Gröbner basis inferred by the gate-level representation of the circuit. We provide a precise formalization of this reasoning process, which includes soundness and completeness arguments and adds to the mathematical background in this field. On the practical side we present an unique incremental column-wise verification algorithm and preprocessing approaches based on variable elimination that simplify the inferred Gröbner basis. Furthermore, we provide an algebraic proof calculus in this thesis that allows obtaining certificates as a by-product of circuit verification in order to boost confidence in the outcomes of automated reasoning tools. These certificates can be efficiently verified with independent proof checking tools.

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Section: Eidesstattliche Erklärungmentioning

confidence: 99%

Formal verification of multiplier circuits using computer algebra

Kaufmann

2022

It - Information Technology

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“…It rewrites the model obtained from XOR rewriting such that the polynomials depend only on variables that are used in more than one polynomial. 2 Another part of the multiplier that shows the efficiency of the proposed XOR rewriting to reveal vanishing monomials is the Booth partial product cell. Although every cell has only one vanishing monomial, canceling it later by GB reduction causes a blow-up.…”

Section: B Rewriting Schemesmentioning

confidence: 99%

“…The most successful techniques up to today are based on reverse engineering an arithmetic bit-level (ABL) representation of the circuit [2] and-more recently-using computer algebra techniques on polynomial representations [3]- [8]. The latter techniques reduce the verification problem to membership testing of the specification polynomial in the ideal spanned by the circuit polynomials.…”

Section: Introductionmentioning

confidence: 99%

Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction

Sayed-Ahmed

Große

Kühne

et al. 2016

Proceedings of the 2016 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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Formal verification utilizing symbolic computer algebra has demonstrated the ability to formally verify large Galois field arithmetic circuits and basic architectures of integer arithmetic circuits. The technique models the circuit as Gröbner basis polynomials and reduces the polynomial equation of the circuit specification wrt. the polynomials model. However, during the Gröbner basis reduction, the technique suffers from exponential blow-up in the size of the polynomials, if it is applied on parallel adders and recoded multipliers. In this paper, we address the reasons of this blow-up and present an approach that allows to apply the technique on basic and complex parallel architectures of multipliers. The approach is based on applying a logic reduction rule during Gröbner basis rewriting. The rule uses structural circuit information to remove terms that evaluate to zero before their blow-up. The experiments show that the approach is applicable up to 128 bit multipliers.

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Formal Verification of Integer Multiplier Circuits Using Algebraic Reasoning: A Survey

Kaufmann

2021

Recent Findings in Boolean Techniques

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Modeling of custom-designed arithmetic components for ABL normalization

Cited by 7 publications

References 10 publications

Formal verification of multiplier circuits using computer algebra

Formal verification of multiplier circuits using computer algebra

Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction

Formal Verification of Integer Multiplier Circuits Using Algebraic Reasoning: A Survey

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