An integrated design environment for performance and dependability analysis

Klenke, Robert H.; Meyassed, M.; Aylor, J.H.; Johnson, B.W.; Rae, R.; Ghosh, Abhijit

doi:10.1145/266021.266061

Cited by 16 publications

(6 citation statements)

References 8 publications

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“…This design environment is based on the ADEPT performance modeling environment [15]. ADEPT is based on the VHSIC Hardware Description Language (VHDL) and provides a modeling environment where high-level models can be refined down to an implementation in an integrated manner.…”

Section: Environment and Model Of Executionmentioning

confidence: 99%

“…The cycle-based modeling constructs support datapath modeling at, or above, the RTL level. In addition, the existing capabilities for mixed-level modeling in ADEPT [15] allow RTL level models to be refined to an actual implementation in a step-wise manner. The modeling levels which are supported by the cycle-based modeling constructs include an abstract system level, an intermediate system/RTL level, and an RTL level.…”

Section: Design Flow and Datapath Controlmentioning

confidence: 99%

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A top-down design environment for developing pipelined datapaths

McGraw

Aylor

Klenke

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

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This paper presents a design environment for cycle-based systems, such as microprocessors, that permits modeling of these systems at various levels, from the abstract system level, through the detailed RTL level, to an actual implementation. The environment allows the models to be refined to lower levels in a step-wise manner. The environment provides the ability to obtain meaningful metrics from abstract models of a processor's architecture. This capability allows design alternatives to be evaluated earlier in the design cycle, thus eliminating costly redesign and reducing the processor time to market. IntroductionCurrently within the design community there is an increasing interest in the development of methodologies which reduce the time to market for a given system under development. One area of particular concern deals with the development of application specific processors [1]. With integrated circuits projected to reach the size of over 100 million transistors per die by the turn of the century [2], this increasing complexity must be handled properly so as not to adversely affect processor design time. One way to address this problem of complexity management is through the use of a top-down design methodology.Top-down design methodologies have been used to design digital hardware design since the early 1970's [3]. A top-down design methodology follows a design from the top level, usually the specification level, of detail down to a detailed implementation. Model refinement in these methodologies works by having each level of detail serve as the design specification for the level of detail immediately below. It is acknowledged that if this hierarchical chain can be verified from one level of detail to the next, the resulting behavioral implementation will be "right the first time" [4]. Being able to develop systems that work on the first pass in a timely manner helps address the time to market problem. Unfortunately, there exists a lack of modeling environments which promote complete top-down design and refinement of processors from the system level.This paper presents a timed cycle-based design environment which is geared toward the development of pipelined datapaths for processors and other synchronous systems. This cycle-based environment permits the processor designer to model and hierarchically refine pipelined processor datapaths from the system level down through the RTL level until a behavioral implementation has been developed. This paper focuses on the modeling and development of pipelined datapaths because most modern processor architectures contain considerable pipelining. The remainder of this paper is organized as follows; Section 2 presents a background of existing processor design environments. Section 3 presents an overview of the new design environment proposed herein. Section 4 describes the intermediate level modeling capability of the environment that provides a link between the abstract system level of modeling and the detailed functional level model. Finally, Section 5 present...

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Section: Environment and Model Of Executionmentioning

confidence: 99%

Section: Design Flow and Datapath Controlmentioning

confidence: 99%

A top-down design environment for developing pipelined datapaths

McGraw

Aylor

Klenke

1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

Self Cite

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“…A number of methodologies [1,5,6,13] have been proposed for effective design space exploration in system synthesis at RT and behavioural levels. Tools for these higher abstraction levels, unlike physical design tools, require heuristics to guide the exploration towards a specific direction.…”

Section: Introductionmentioning

confidence: 99%

“…Besides that, accurate estimation is even more important when the design process is started at a higher level of abstraction. Decisions made during initial phases of system level synthesis determine up to 80% of the final cost [13].…”

Section: Introductionmentioning

confidence: 99%

Evaluation of design space exploration strategies

Moya

López

1999

Proceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium

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The design space exploration (DSE) subsystem of a design automation tool is responsible for early identification of interesting zones of the design space.Evaluation of the exploration strategy used in a tool is extremely difficult because there is not enough information about either the design space or the actual cost function. This paper describes a software environment for quantitative evaluation of isolated exploration algorithms based on a completely simulated framework. A simple model of the design space allows easy representation of interesting properties of exploration algorithms.

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“…MEFISTO [26] and VERIFY [39] are simulation-based fault injection tools which can inject faults into VHDL models of systems. ADEPT [32] is a simulation-based tool, which can evaluate the dependability parameters of a system using VHDL models. However ADEPT is not a fault injection tool.…”

Section: Comparison Of the Fault Injection Techniquesmentioning

confidence: 99%

A hybrid fault injection approach based on simulation and emulation co-operation

Ejlali

Miremadi²,

Zarandi³

et al.

2003 International Conference on Dependable Systems and Networks, 2003. Proceedings.

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This paper presents a new fault injection approach, which is based on a co-operation between a simulator and an emulator. This hybrid approach utilizes the advantages of both simulation-based fault injection as well as physical fault injection to provide a good controllability, observability and also a high speed in the fault injection experiments. To do this, parts of a circuit are simulated while the rest parts of the circuit are emulated. A fault injection tool called FITSEC (Fault Injection Tool based on Simulation and Emulation Cooperation) is developed, which supports the entire process of a system design. This is based on both Verilog and VHDL languages and can be used to inject faults at different levels of abstraction. The experimental resultsshow that this approach can significantly reduce the time needed for executing fault injection campaigns.

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An integrated design environment for performance and dependability analysis

Abstract: This paper presents a integrated design environment that supports the design and analysis of

Cited by 16 publications

References 8 publications

A top-down design environment for developing pipelined datapaths

A top-down design environment for developing pipelined datapaths

Evaluation of design space exploration strategies

A hybrid fault injection approach based on simulation and emulation co-operation

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