An Integrated Framework for Energy Optimization of Embedded Real-Time Applications

Takase, Hideki; Zeng, Gang; Gauthier, Lovic; Kawashima, Hirotaka; Atsumi, Noritoshi; Tomohiro, Tatematsu; Kobayashi, Yasuhiko; Koshiro, Takenori; Ishihara, Tohru; Tomiyama, Hiroyuki; Takada, Hiroaki

doi:10.1587/transfun.e97.a.2477

Cited by 3 publications

(1 citation statement)

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“…Minimization of power consumption has become an important aspect in the overall system design [3,4]. Application mapping onto a NoC platform is the first step in the generic synthesis flow.…”

Section: Introductionmentioning

confidence: 99%

A novel two-phase heuristic for application mapping onto mesh-based Network-on-Chip

Wang

Liu

et al. 2016

IEICE Electron. Express

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With the growing complexity of embedded VLSI products, traditional System-on-Chip (SoC) are facing severe challenges in the aspects of communicating speed and scalability. Network-on-Chip (NoC) has emerged as a viable alternative. In NoC design, application mapping is one of the most holistic researching dimensions, which maps the cores in the application to the routers in the NoC platform. Application mapping problem usually aims to reduce communication cost and power consumption of the overall system. In this paper, we focus on application mapping onto mesh network, and propose a novel two-phase heuristic algorithm. The first phase attempts to explore the potential searching spaces, while the second phase focuses on exploiting the local optima within the searching basin. To verify the effectiveness of the algorithm, this paper performs a quantitative comparisons between our proposed method and the existing mapping methods under both real application and custom generated application benchmarks.

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Section: Introductionmentioning

confidence: 99%