An integrated optimization framework for reducing the energy consumption of embedded real-time applications

Takase, Hideki; Zeng, Liangen; Gauthier,; Kawashima,; Atsumi, Noritoshi; Tatematsu,; Kobayashi, Yo; Kohara,; Koshiro,; Ishihara, Tohru; Tomiyama,; Takada,

doi:10.1109/islped.2011.5993648

Cited by 6 publications

(6 citation statements)

References 13 publications

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“…The framework uses the energy and performance characteristics of the application for optimizing the energy consumption of the entire system. Figure 1 depicts the workflow of the integrated optimizac 2012 Information Processing Society of Japan tion framework [3] that has been implemented with a complete toolchain and real-time operationg system (RTOS) for automatic energy optimization. The framework consists of three analysis and optimization phases.…”

Section: Overview Of Deps Frameworkmentioning

confidence: 99%

“…In the DEPS framework, we estimate energy consumption and execution time by using execution trace logs generated by a cycleaccurate simulator [2], [3]. A naive approach for generating the DEPS profile is to operate this simulation with all test data and all configuration sets.…”

Section: Cp-interval Data Setupmentioning

confidence: 99%

“…The checkpoint CP0 is always placed at the beginning of a program. The other checkpoints are inserted according to the result of the CP insertion [3]. As can be seen, the same program executes different paths and checkpoints that are dependent on given test data.…”

Section: Cp-interval Data Setupmentioning

confidence: 99%

“…To make best use of such processors, we have proposed dynamic energy performance scaling (DEPS) [2], a generalization of DVFS, and integrated it into a framework for energy optimization of embedded real-time applications [3]. DVFS controls only supply voltage and operating frequency for saving energy, whereas DEPS aims to control more configuration parameters to further reduce energy consumption.…”

Section: Introductionmentioning

confidence: 99%

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Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework

Kawashima

Zeng

Takase

et al. 2012

IPSJ Transactions on System LSI Design Methodology

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A dynamic energy performance scaling (DEPS) framework has been proposed as a generalization of dynamic voltage frequency scaling (DVFS). The DEPS framework selects an energy-optimal hardware configuration at runtime. To reduce runtime overhead, Pareto-optimal combinations of hardware configurations should be provided via DEPS profiling during the design phase. The challenge of DEPS profiling lies in extracting the Pareto-optimal combinations efficiently from the exponential search space. We propose two exact algorithms to reduce the number of calculations in DEPS profiling. These algorithms can be used with common search algorithms. We also propose a heuristic algorithm for searching Pareto-optimal configurations efficiently. Extensive experiments are performed, and they demonstrate that the proposed algorithms can complete DEPS profiling within a reasonable amount of time and generate optimal DEPS profiles. It is believed that the proposed algorithms will enable easy application of the DEPS framework in practice.

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Section: Overview Of Deps Frameworkmentioning

confidence: 99%

Section: Cp-interval Data Setupmentioning

confidence: 99%

Section: Cp-interval Data Setupmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework

Kawashima

Zeng

Takase

et al. 2012

IPSJ Transactions on System LSI Design Methodology

Self Cite

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“…Minimization of power consumption has become an important aspect in the overall system design [3,4]. Application mapping onto a NoC platform is the first step in the generic synthesis flow.…”

Section: Introductionmentioning

confidence: 99%

A novel two-phase heuristic for application mapping onto mesh-based Network-on-Chip

Wang

Liu

et al. 2016

IEICE Electron. Express

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With the growing complexity of embedded VLSI products, traditional System-on-Chip (SoC) are facing severe challenges in the aspects of communicating speed and scalability. Network-on-Chip (NoC) has emerged as a viable alternative. In NoC design, application mapping is one of the most holistic researching dimensions, which maps the cores in the application to the routers in the NoC platform. Application mapping problem usually aims to reduce communication cost and power consumption of the overall system. In this paper, we focus on application mapping onto mesh network, and propose a novel two-phase heuristic algorithm. The first phase attempts to explore the potential searching spaces, while the second phase focuses on exploiting the local optima within the searching basin. To verify the effectiveness of the algorithm, this paper performs a quantitative comparisons between our proposed method and the existing mapping methods under both real application and custom generated application benchmarks.

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An Energy Efficient Embedded Processor for Hard Real-Time Java Applications

Tewary

Malik

Salčić

et al. 2019

Architecture of Computing Systems – ARCS 2019

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An integrated optimization framework for reducing the energy consumption of embedded real-time applications

Cited by 6 publications

References 13 publications

Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework

Efficient Algorithms for Extracting Pareto-optimal Hardware Configurations in DEPS Framework

A novel two-phase heuristic for application mapping onto mesh-based Network-on-Chip

An Energy Efficient Embedded Processor for Hard Real-Time Java Applications

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